Mentor Graphics Corporation

Other

Siemens Industry Software Gmbh

Robert A Todd

Patrick D Gibson

Michael C McSherry

Richard E Strobel

Laurence W Grodd

George P Lippincott

Jea Woo Park

Jimmy Jason Tomblin

Paul M Nguyen

Nick Cobb

Jimmy J Tomblin

Paul M Nugyen

A system may include a set of compute engines. The compute engines may be configured to perform electronic design automation (EDA) operations on a hierarchical dataset representative of an integrated circuit (IC) design. The system may also include a dynamic resource balancing engine configured to allocate computing resources to the set of compute engines and reallocate a particular computing resource allocated to a first compute engine based on an operation priority of an EDA operation performed by a second compute engine, an idle indicator for the first compute engine, or a combination of both.

Dynamic allocation of computing resources for electronic design automation operations

A system may include a resource acquisition engine configured to acquire a set of computing resources for execution of an application flow comprising multiple invocations to an EDA application. The system may also include a resource provision engine configured to provide the set of computing resources for execution of a first EDA process of the EDA application launched by a first invocation in the application flow and identify a second invocation subsequent to the first invocation in the application flow, the second invocation to launch a second EDA process of the EDA application. The resource provision engine may be further configured to, without releasing the set of computing resources provided to the first EDA process, proxy the set of computing resources into a proxied set of computing resources and provide the proxied set of computing resources for execution of the second EDA process of the EDA application.

Resource provisioning for multiple invocations to an electronic design automation application

A computing system may include an electronic design automation (EDA) data constructor engine and an EDA executor engine. The EDA data constructor engine may be configured to perform, using the local resources of the computing system, a data preparation phase of an EDA procedure for a circuit design. The EDA executor engine may be configured to acquire remote resources for an execution phase of the EDA procedure, wherein the remote resources include remote compute resources and remote data resources remote to the computing system; broadcast constructor data constructed from the data preparation phase of the EDA procedure to the acquired remote data resources; and manage performance of the execution phase of the EDA procedure by the acquired remote compute resources and remote data resources.

Hybrid performance of electronic design automation (EDA) procedures with delayed acquisition of remote resources

A system may include a pool of heterogeneous compute units configured to execute an electronic design automation (EDA) application for design or verification of a circuit, wherein the pool of heterogeneous compute units includes compute units with differing computing capabilities. The system may also include a resource utilization engine configured to identify an EDA operation to be performed for the EDA application, select a compute unit among the pool of heterogeneous compute units to execute the EDA operation based on a determined computing capability specific to the selected compute unit, and assign execution of the EDA operation to the selected compute unit.

Resource utilization of heterogeneous compute units in electronic design automation

Aspects of the disclosed technology relate to techniques of pattern matching. Matching rectangles in a layout design that match rectangle members of a search pattern are identified based on edge operations. The rectangle members comprise an origin rectangle member and one or more reference rectangle members. Grid element identification values are attached to the matching rectangles. The matching rectangles that match the one or more reference rectangle members in neighborhoods of the matching rectangles that match the origin rectangle member are then analyzed. The neighborhoods are determined based on the grid element identification values. Based on the analysis, matching patterns in the layout design that match the search pattern are determined.

Pattern matching using edge-driven dissected rectangles

One or more control points are identified within a reticle layout that is used in a simulation of a manufacturing process for an integrated device layer. Further, a current geometrical layout pattern is determined in the vicinity of the control points, and a cache is searched for a matching geometrical layout pattern. If the search is successful, a simulation result associated with the matching geometrical layout pattern is retrieved from the cache and reused for the current geometrical layout pattern. Alternatively, if the search is unsuccessful, a simulation result associated with the current geometrical design pattern is computed and stored in the cache for future reuse.

Caching of lithography and etch simulation results

A parasitic extraction tool (PEX) is provided to generate electrical modeling data for an integrated circuit (IC) design, e.g. a deep sub-micron IC design. The PEX includes a read function for reading extracted connectivity and geometrical data of various layout cell hierarchies of the IC design, that are organized and indexed by layout nets. The PEX also includes a write function for writing generated electrical modeling data into a parasitic database (PDB), which is physically organized to accommodate physical storage of the electrical modeling data in multiple physical media, and concurrent usage of the electrical data by multiple client applications, e.g. post layout analysis tool. In one embodiment, the PDB further includes an application interface that shields the physical organization of the PDB, and a logical abstraction of the physical organization to facilitate implementation of the application interface.

Method and apparatus for generating and maintaining electrical modeling data for a deep sub-micron integrated circuit design

A data extraction tool is provided to extract filtered connectivity and geometrical data for specified layout cell hierarchies of an integrated circuit (IC) design, e.g. a deep sub-micron IC design. The connectivity and geometrical data for each layout cell hierarchy are extracted at least in part in accordance with specified parasitic effect windows. In one embodiment, the data extraction tool includes a filtered extraction function that operates to extract connectivity and geometrical data for layout nets of each layout cell hierarchy of the IC design, one or more layout nets at a time. Additionally, one or more filtered databases are provided to store the filtered connectivity and geometrical data of the layout cell hierarchies.

Method and apparatus for extracting and storing connectivity and geometrical data for a deep sub-micron integrated circuit design

Boat tower

Porous friction facing materials containing cellulose fibers are coated with an impregnant of ethyl silicate to provide automatic transmission clutch plate and band linings of improved frictional properties, durability, wear and heat resistance, without use of asbestos. A sheet of paper-like fibrous material may be first impregnated with a phenolic resin binder which is cured to form a first coating and then impregnated with a hydrolyzed solution of ethyl silicate in a solvent. The material is further heated to drive off the solvent and cure the ethyl silicate to form a second outer coating having a higher coefficient of friction than the first coating. The silicate impregnated lining is then bonded to the steel plate or band. Alternatively, the resin impregnated lining material may be first bonded to the metal plate and then the entire plate assembly is impregnated with the ethyl silicate solution and cured.

Growing community of inventors

Beaverton, OR, United States of America

Robert A Todd