Emc Corporation

Robert A Thibault

Stephen D MacArthur

David Lionel Black

Brian William Gallagher

Avinash Kallat

Richard Wheeler

Yuval Ofek

John K Walton

Christopher S MacLellan

Daniel Castel

Paul C Wilson

Michael Shulman

William R Tuccio

Mark Zani

Farouk Khan

Stephen D Macarthur

Steven MacArthur

Kendall A Chilton

Brian Marchionni

A system interface includes a plurality of first directors, a plurality of second directors, a data transfer section and a message network. The data transfer section includes a cache memory. The cache memory is coupled to the plurality of first and second directors. The messaging network operates independently of the data transfer section and such network is coupled to the plurality of first directors and the plurality of second directors. The first and second directors control data transfer between the first directors and the second directors in response to messages passing between the first directors and the second directors through the messaging network to facilitate data transfer between first directors and the second directors. The data passes through the cache memory in the data transfer section. A method for operating a data storage system adapted to transfer data between a host computer/server and a bank of disk drives. The method includes transferring messages through a messaging network with the data being transferred between the host computer/server and the bank of disk drives through a cache memory, such message network being independent of the cache memory.

Data storage system having separate data transfer section and message network

Method for message transfer in computer storage system

Data storage system having point-to-point configuration

A system interface includes a plurality of first director boards. Each one of the first director boards has a plurality of first directors and a crossbar switch having input/output ports coupled to the first directors on such one of the first director boards and a pair of output/input ports. The system interface also includes a plurality of second director boards. Each one of the second directors boards has a plurality of second directors and a crossbar switch having input/output ports coupled to the second directors on such one of the second director boards and a pair of output/input ports. A data transfer section is provided having a cache memory. The cache memory is coupled to the plurality of first and second directors. A message network is operative independently of the data transfer section. The message network includes a pair of message network boards. Each one of such message network boards has a switching network having a plurality input/output ports. Each one of such pair of input/output ports is coupled to a corresponding one of the pair of output/input ports of the crossbar switches of the plurality of first director boards and the plurality of second director boards. The first and second directors control data transfer between the first directors and the second directors in response to messages passing between the first directors and the second directors through the message network to facilitate data transfer between first directors and the second directors. Data passes through the cache memory in the data transfer section. Each one of the directors includes: a data pipe coupled between an input of such one of the second directors and the cache memory; a microprocessor. A controller is coupled to the microprocessor and the data pipe for controlling the transfer of the messages between the message network and such one of the second directors and for controlling the data between the input of such one of the second directors and the cache memory.

Data storage system having separate data transfer section and message network with plural directors on a common printed circuit board and redundant switching networks

A method and system for producing a data storage system for transferring data between a host computer/server and a bank of disk drives through a system interface. The system interface has a plurality of first directors, a plurality of second directors, and a global memory. The method includes: providing a backplane having slots adapted to have plugged therein a plurality of printed circuit board. The printed circuit boards include: a plurality of first director boards having the first directors; a plurality of second printed circuit boards having the second directors; a plurality of memory printed circuit boards providing the global memory; a plurality of dummy first director boards having first jumpers; a plurality of dummy second director boards having second jumpers; a plurality of dummy memory boards having third jumpers. The method includes wiring the backplane to effect a connection among the first, second and third jumpers to interconnect the first plurality of director to the host computer/server, the plurality of second plurality of directors to the bank of disk drives and the global memory to the first plurality of directors and to the second plurality of director. The method and system allows the same wired backplane to be used with systems having a different number of memory and director boards and still enable dual-write and redundancy to the global memory.

Data storage system having dummy printed circuit boards with jumpers

Data storage system having dummy printed circuit boards

A data storage system for transferring data between a host computer/server and a bank of disk drives through a system interface. The system interface includes: a plurality of first directors coupled to the host computer/server; a plurality of second directors coupled to the bank of disk drives; a cache memory; and a data transfer section coupled to the plurality of first directors, the second directors, and the cache memory. A messaging network is coupled to the plurality of first directors and the plurality of second directors. The first and second directors control data transfer between the host computer and the bank of disk drives in response to messages passing between the directors through the messaging network as such data passes through the memory via the data transfer section. A service processing network is provided for interfacing a plurality of service processing units to the plurality of first and second directors through a plurality of redundant communication channels. With such arrangement, because the service processor is being more involved in the functionality operation of the system, a pair of redundant service processors is provided. This thereby improves the reliability of the system including those system functions controlled by the service processor.

Data storage system having redundant service processors

Data storage system having separate data transfer section and message network with status register

Data storage system having separate data transfer section and message network with bus arbitration

A direct memory access (DMA) transmitter includes: (a) a data register; and (b) a transmitter state machine. Requested data at an address provided by a source is read from the random access memory then transferred for storage in the data register. The central processing unit also sends a control signal to the transmit state machine. The control signal indicates to the transmit state machine whether the read data is a most recent copy of the requested data in random access memory or whether the most recent copy of the requested data is still resident in the local cache memory. In response to the control signal, if the most recent data is in the local cache memory, the transmit state machine inhibits the data that was read from random access memory and now stored in data register from passing to the transmitter output. Transmit state machine then performs a second data transfer request at the same address, the second requested data being transferred from the local cache memory to the random access memory. The transmit state machine reads the second requested data from the random access memory. The second requested data is the most recent data available in the random access memory. The transmit state machine then stores such second requested data into the data register, such stored second requested data then being transferred to the transmitter output.

Direct memory access (DMA) transmitter

A direct memory access (DMA) receiver adapted to receive data from a source, such data to be written into a random access memory is provided. The random access memory and DMA receiver being coupled are to a central processing unit by a bus. The central processing unit is coupled to a local cache memory. The source of such data provides an address for the data, such address being the location the random access memory where the data is to be stored. The DMA receiver includes an address register, a first data register and a duplicate data register. The duplicate register has an input coupled to an output of the first data register. A selector is provided having a pair of inputs, one being coupled to the output of the first data register and another one of the pair of inputs being coupled to an output of the duplicate data register. The selector couples one of the pair of inputs to an output thereof selectively in accordance with a select signal. A state machine is included in the DMA receiver. The state machine is responsive to a receive write enable signal from the source. In response to such signal, the state machine loads the address into the address register and loads the data into the first data register transferring the data onto the bus for storage in the random access memory at the address loaded into the address register. The state machine also checks to determine whether the data corresponding to the address being written into the random access memory is currently stored in the local cache memory. The state machine also transfers the data in the first data register into the duplicate data register. If the data is located in the local cache memory, the state machine waits for the central processing unit to copy data in the local cache memory to the addresses in the random access memory, produces the select signal to couple the data in the duplicate data register to the bus, and overwrites the data in the local cache memory with the data provided on the bus by the duplicate data register.

Direct memory access (DMA) receiver

A computer storage system includes an array of storage devices, a system cache memory, one or more back end directors for controlling data transfer between the storage devices and the system cache memory, and one or more front end directors for controlling data transfer between the system cache memory and a host computer. Each director includes a processor and a message interface for controlling high speed message transfer between the processors in the directors. The message interfaces in the directors may be interconnected in a closed-loop configuration. Each message interface may include a transmit/receive circuit for transferring messages to and from other directors, a message memory for storing outgoing messages and incoming messages, and a message controller for controlling transfer of messages between the processor and the message memory and between the message memory and the transmit/receive circuit.

Methods and apparatus for message transfer in computer storage system

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Raynham, MA, United States of America

Robert A Thibault