Motorola Corporation

Freescale Semiconductor,inc.

Nxp Usa, Inc.

Robert A Pryor

Wayne R Burger

Xiaowei Ren

Michael G Coleman

Israel A Lesk

Paul W Sanders

Thuy B Dao

Michael F Petras

Joel E Keys

John L Freeman, Jr

Raymond J Balda

Michael C Keeling

William L Bailey

Robert J Johnsen

Jeffrey Kevin Jones

Margaret A Szymanowski

Audel Sanchez

Joseph Gerard Schultz

David Cobb Burdeaux

Philippe Renaud

Daniel J Lamey

Zihao M Gao

Christopher Paul Dragon

Michele Lynn Miera

Neil T Tracht

Jose Luis Suarez

Lawrence A Grenon

Kurt K Sakamoto

James D Paulsen

Fabio Restrepo

Joseph L Petrucci, Jr

Kimberly J Foxx

Low Q associated with passive components of monolithic integrated circuits (ICs) when operated at microwave frequencies can be avoided or mitigated using high resistivity (e.g., &#x2267;100 Ohm-cm) semiconductor substrates and lower resistance inductors for the IC. This eliminates significant in-substrate electromagnetic coupling losses from planar inductors and interconnections overlying the substrate. The active transistor(s) are formed in the substrate proximate the front face. Planar capacitors are also formed over the front face of the substrate. Various terminals of the transistor(s), capacitor(s) and inductor(s) are coupled to a ground plane on the rear face of the substrate using through-substrate-vias to minimize parasitic resistance. Parasitic resistance associated with the planar inductors and heavy current carrying conductors is minimized by placing them on the outer surface of the IC where they can be made substantially thicker and of lower resistance. The result is a monolithic microwave IC previously unobtainable.

Monolithic microwave integrated circuits

The embodiments described herein provide a die crack detector and method that use a conductive trace arranged to at least substantially extend around a perimeter of an integrated circuit die. A one-time programmable element, such as a fuse, is coupled in series with the conductive trace, and a package lead is electrically coupled to both the fuse and another operational element on the integrated circuit die. With the fuse intact the package lead can thus be used to determine a measurement of the conductivity of the conductive trace, with the measurement of conductivity indicative of the presence of a crack on the die. After such testing the fuse can be electrically opened, and the package lead used for normal operation of the device on the packaged die without the conductive trace interfering with this operation.

Die crack detector with integrated one-time programmable element

An embodiment of a packaged RF amplifier device includes a device substrate, a transistor die coupled to the device substrate, and an isolation structure coupled to the transistor die. The transistor die has a top die surface, a bottom die surface, a semiconductor substrate, first and second transistors formed in the semiconductor substrate, a conductive structure at the top die surface and positioned between the first and second transistors, and a low resistance path that extends vertically through the semiconductor substrate between the conductive structure and the bottom die surface. The isolation structure is coupled to the conductive structure and extends into an area above the top die surface between the first and second transistors. The isolation structure may be a wirebond fence, a conductive wall, conductive pillars or vias, or a plated trench that extends vertically upward from the conductive structure. The device may be encapsulated with molding compound.

Packaged RF amplifier devices with grounded isolation structures and methods of manufacture thereof

A device includes a semiconductor substrate having a surface with a trench, first and second conduction terminals supported by the semiconductor substrate, a control electrode supported by the semiconductor substrate between the first and second conduction terminals and configured to control flow of charge carriers during operation between the first and second conduction terminals, and a Faraday shield supported by the semiconductor substrate and disposed between the control electrode and the second conduction terminal. At least a portion of the Faraday shield is disposed in the trench.

Trenched Faraday shielding

Low Q associated with passive components of monolithic integrated circuits (ICs) when operated at microwave frequencies can be avoided or mitigated using high resistivity (e.g., &#x2267;100 Ohm-cm) semiconductor substrates and lower resistance inductors for the IC. This eliminates significant in-substrate electromagnetic coupling losses from planar inductors and interconnections overlying the substrate. The active transistor(s) are formed in the substrate proximate the front face. Planar capacitors are also formed over the front face () of the substrate. Various terminals of the transistor(s), capacitor(s) and inductor(s) are coupled to a ground plane on the rear face of the substrate using through-substrate-vias to minimize parasitic resistance. Parasitic resistance associated with the planar inductors and heavy current carrying conductors is minimized by placing them on the outer surface of the IC where they can be made substantially thicker and of lower resistance. The result is a monolithic microwave IC previously unobtainable.

Methods of making a monolithic microwave integrated circuit

A multiple-path, configurable, radio-frequency (RF) circuit is provided, including: a first amplifier path amplify a first RF signal to generate a first amplified signal; a second amplifier path configured to amplify a second RF signal to generate a second amplified signal; a corrective input matching circuit, configured to change first input-impedance-matching properties of the first amplifier path, and to change second input-impedance-matching properties of the second amplifier path; a first isolation element configured to selectively ground an input node of the second amplifier path; a second isolation element configured to selectively ground an output node of the second amplifier path; and a third isolation element connected between the first and second amplifier paths, configured to selectively isolate the corrective input matching circuit from first and second input nodes of the first and second amplifier paths, respectively, or connect the corrective input matching circuit to the first and second input nodes.

Configurable power amplifier and related construction method

Low Q associated with passive components of monolithic integrated circuits (ICs) when operated at microwave frequencies can be avoided or mitigated using high resistivity (e.g., &#x2267;100 Ohm-cm) semiconductor substrates () and lower resistance inductors (') for the IC (). This eliminates significant in-substrate electromagnetic coupling losses from planar inductors () and interconnections (--&#x2033;) overlying the substrate (). The active transistor(s) (&#x2032;) are formed in the substrate () proximate the front face (). Planar capacitors (&#x2032;) are also formed over the front face () of the substrate (). Various terminals (------&#x2032;, etc.) of the transistor(s) (&#x2032;), capacitor(s) (&#x2032;) and inductor(s) (&#x2032;) are coupled to a ground plane () on the rear face () of the substrate () using through-substrate-vias (&#x2032;) to minimize parasitic resistance. Parasitic resistance associated with the planar inductors (&#x2032;) and heavy current carrying conductors (-&#x2032;) is minimized by placing them on the outer surface of the IC where they can be made substantially thicker and of lower resistance. The result is a monolithic microwave IC () previously unobtainable.

Monolithic microwave integrated circuit

An RF power transistor with a metal design () comprises a drain pad () and a plurality of metal drain fingers () extending from the drain pad, wherein at least one metal drain finger comprises one or more sections of metal (-----), each section of metal including of one or more branch (-------) of metal having a metal width maintained within a bamboo regime.

RF power transistor device with metal electromigration design and method thereof

A semiconductor device, such as a RF LDMOS, having a ground shield that has a pair of stacked metal layers. The first metal layer extends along the length of the semiconductor device and is formed on the upper surface of the semiconductor device body. The first layer has a series of regularly spaced apart lateral first slots. The second metal layer, coextensive with and located above the first metal layer, has a series of regularly spaced apart lateral second slots. The second slots overlie the spaces between the first slots, and the continuous portions of the second metal layer overlie the first slots. The slots are substantially parallel to wires extending over the ground shield. The ground shield is not limited to only two metal layers. The ground shield has a repeating unit design that facilitates automated design.

Ground shields for semiconductors

In a semiconductor manufacturing method, an emitter region () and a base enhancement region () are formed to provide linear voltage, capacitance and low resistance characteristics. In the manufacturing method, a semiconductor device () is formed on a silicon substrate layer () with an epitaxial layer (). Trenches () are cut into the epitaxial layer () and filled with oxide () to provide reduced junction capacitance and reduced base resistance. The emitter region () and the base enhancement region () are simultaneously formed through an anneal process.

Semiconductor device and method of manufacture

A method of manufacturing a semiconductor component includes providing a composite substrate ( ) with a dielectric portion and a semiconductor portion and growing an epitaxial layer ( ) over the composite substrate. The epitaxial layer has a polycrystalline portion ( ) over the dielectric portion of the composite substrate and also has a monocrystalline portion ( ) over the semiconductor portion of the composite substrate. A first dopant is diffused into the monocrystalline portion of the epitaxial layer to form an emitter region in the monocrystalline portion of the epitaxial layer while a second dopant is simultaneously diffused into the monocrystalline portion of the epitaxial layer to form an enhanced portion of the base region.

Method of manufacturing a semiconductor component

A capacitor (58) for an integrated circuit having a conductive trench (50), disposed below a bottom electrode layer (52), that electrically connects the bottom electrode layer to a semiconductor substrate (14, 16). The conductive trench eliminates the need for a top-side contact to the bottom electrode layer. The semiconductor substrate is, for example, connected to ground.

Integrated circuit capacitor having a conductive trench

An interconnection system for interconnecting a plurality of photovoltaic devices. The photovoltaic devices each have a first and a second side and the interconnect system is located on the second side of the photovoltaic devices. A sheet of dielectric material and a sheet of electrically conductive material are bonded together and positioned so that the dielectric material is next to the photovoltaic devices. A plurality of patterns are formed in the sheet of electrically conductive material. The patterns each have angled tabs punched therein so that the angled tabs are punched through both the electrically conductive material and the dielectric material. When a photovoltaic device is positioned within a group of angled tabs, the angled tabs can be brought into contact with electrical contacts on the first side of the photovoltaic device. The group of angled tabs are electrically common to a part of the pattern which has an extended portion which extends beneath an adjacent photovoltaic device. Some of the dielectric material is removed from the extended portion so that this portion then makes contact with the second side of an adjacent photovoltaic device. The patterns can be formed in predetermined configurations to provide series or series-parallel interconnections for photovoltaic devices within an array of photovoltaic devices. The interconnect system, in turn, provides for substantially all possible series, parallel, or series-parallel interconnections of a plurality of arrays.

Method for interconnecting photovoltaic devices

An improved solar energy device has a body of semiconductor material of a first conductivity type with a region of a second conductivity type formed in the body and extending to its surface. A current collection metallization pattern is disposed on the second conductivity type region, with at least three distinct and identifiable current accumulation points connected to the metallization pattern adjacent to the periphery of the second conductivity type region. External electrical connection is made to extract available electrical power from the device at the current accumulation points. The periphery of the device is free of other electrically equivalent external electrical connection areas. These features allow a substantial increase in device efficiency.

Contact for solar cells

A semiconductor cell for generating current in response to incident radiation, particularly solar energy, wherein a layer of material having charges is disposed over the PN current generating junction. The layer having charges possesses a net bound charge of the same polarity as the minority carriers associated with the underlying semiconductor material for aiding minority carrier flow across the PN junction and for minimizing recombination of those minority carriers at the surface of the semiconductor body.

Growing community of inventors

Mesa, AZ, United States of America

Robert A Pryor