National Semiconductor Corporation

Other

Robert A Pease

James V Ball

Robin Shields

Sean S Chen

Robert C Dobkin

Jonathan Klein

Jay Friedman

Mansour Izadinia

The present invention covers novel approaches to the differential amplification of an input signal. Embodiments of the present invention have precise gain, swing to within micro-volts (&#x3bc;V) of ground, and have high CMRR without the need for precision resistors or tuned potentiometers. Embodiments of the present invention are particularly suited for the amplification of an instrumentation signal for delivery to an analog-to-digital converter. Examples of such signals include the product of a strain-gauge front end, a temperature sensor front end, and certain devices for bioelectronics detection. Embodiments of the present invention which are systems for amplification of a differential input signal can comprise a differential input stage transconducing a differential voltage input signal into a single-ended intermediate current signal using a follower transconductance amplifier, and a single-ended output stage comprising an amplifier producing an output voltage across a resistor network that forms a negative feedback network of the amplifier.

Differential amplifier with improved zero-point calibration

A current source for providing matched currents at low and variable bias voltages. The current source includes a first circuit, a second circuit, and a biasing circuit. The first circuit provides a first current. The first circuit includes a first transistor with a control terminal, a first terminal, and second terminal. A second circuit provides an output current to an output node. The second circuit includes a second transistor with a control terminal, a first terminal, and second terminal. The biasing circuit includes a third transistor with a control terminal, a first terminal, and second terminal. The biasing circuit also includes a fourth transistor with a control terminal, a first terminal, and second terminal. The biasing circuit provides a voltage at the first terminal of the third transistor and a voltage at the control terminal of the second transistor so that a voltage at the first terminal of the second transistor and a voltage at the second terminal of the first transistor match. Thereby, the first current and output current approximately match.

Ultra low voltage cascode current mirror

A temperature stabilized, constant current source of the present invention includes a feedback control stage that provides a substantially constant battery charging current at a particular temperature. A temperature stabilized current source stage includes a negative temperature coefficient current source that provides a countervailing control current to a positive temperature coefficient current source that is coupled from a sensing resistor. The temperature dependencies of the positive and negative temperature coefficient current sources tend to cancel each other out so as to provide a temperature stabilized current to the sensing resistor. In this way, a control voltage is developed across the control resistor that is independent of resistor temperature dependencies.

Temperature stabilized constant current source suitable for charging a highly discharged battery

A temperature sensor circuit generates an output voltage that is linearly proportional to temperature over a desired temperature range with a desired offset voltage. The temperature sensor includes two Proportional To Absolute Temperature (PTAT) current sources that generate PTAT currents and two transistors which conduct the PTAT currents with different current densities to establish a basic voltage PTAT across a resistor. An offset resistor coupled between the bases of the two transistors and a circuit node, shifts the basic PTAT voltage by an offset voltage. A first gain circuit couples to the collector of the first transistor and the offset resistor and generates a servo current (i.e., a current that tends to move the circuit to the desired state by correcting an error) to servo the base of the first transistor when there is a difference between the first transistor's collector current and the PTAT current. A second gain circuit generates a second servo current to servo the emitter of the second transistor when there is a difference between the second transistor's collector current and the PTAT current. These servo currents drive the two transistors such that the second gain circuit generates a temperature related output voltage shifted from the basic voltage PTAT by the offset voltage, and which follows a predetermined temperature scale and has a substantially linear function with a desired offset temperature.

Temperature sensor to run from power supply, 0.9 to 12 volts

Ultra low voltage cascoded current sources

A current regulator includes a regulation stage and a start-up stage. The regulation stage has a base bus and an output transistor having a base coupled to the base bus for generating a regulated current. The regulation stage also includes a current maintaining transistor coupled to the base bus for inducing and maintaining an operating current in the base bus in response to a start-up current first being induced in the base bus. The start-up stage includes a start-up transistor coupled to the base bus for inducing the start-up current in the base bus before the current maintaining transistor is turned on. The start-up transistor is turned off by the regulation stage after the current maintaining transistor is maintaining the operating current in the base bus. A method of starting-up a regulator circuit includes the steps of: establishing a base bus; inducing a start-up current in the base bus; inducing an operating current in the base bus; establishing a conduction path between an emitter of a current maintaining transistor and an emitter of a start-up transistor; and gradually increasing a current which flows through the conduction path in order to gradually decrease a current conducted by the start-up transistor in order to turn the start-up transistor off.

Current regulator having start-up circuitry which is turned off after

A preferred embodiment of an integrated semiconductor device includes a semiconductor die having a hole therethrough. A paddle member includes a handle member connected between the paddle member and the semiconductor die to suspend the paddle member in the hole. A cap layer is bonded to the semiconductor die to completely cover the hole, the paddle member, and the handle member. The second surface of the semiconductor die is bonded to the lead frame. A preferred embodiment of a method of manufacturing an integrated semiconductor device includes the steps of: forming a semiconductor die having a paddle area for isolating sensitive circuitry and an unoccupied area which substantially surrounds the paddle area except for a handle area, forming a trench in the unoccupied area, covering the paddle area, the trench, and the handle area with a sacrificial spacer material, covering the sacrificial spacer material with a cap layer, etching the semiconductor die beneath the paddle area and the trench until the handle area suspends the paddle area within a hole formed in the semiconductor die, and bonding the second surface of the semiconductor die to a lead frame.

Apparatus for achieving mechanical and thermal isolation of portions of

A protection circuit for a semiconductor switch for switching a load is disclosed. Control circuitry is used for switching the semiconductor switch on in response to a switching signal and for switching the semiconductor switch off in response to a deactivation signal. A deactivation circuit is used for generating the deactivation signal. An overvoltage detector circuit responsive to a voltage at an output of the semiconductor switch that exceeds a predetermined value is used for generating an overvoltage signal. The overvoltage detector circuit includes a Zener diode that has its cathode coupled through a resistor to the output of the semiconductor switch and its anode coupled to the collector of the diode connected transistor. A first logic circuit is used for causing the deactivation circuit to generate the deactivation signal in response to the switching signal and the overvoltage signal. The first logic circuit includes a first npn transistor that has its base coupled through a resistor to receive the switching signal. A second npn transistor receives the overvoltage signal through a resistor at its base. The collector of the first npn transistor is coupled to the collector of the second npn transistor. A third npn transistor has its base coupled to the collector of the second npn transistor. A first pnp transistor has its base coupled to the collector of the third npn transistor. One of the two collectors is coupled to the deactivation circuit.

Protection circuit used for deactivating a transistor during a

Logic circuit capable of handling large input current

Apparatus and method for achieving mechanical and thermal isolation of

An integrated circuit is shown in which provision is made for terminating or locking out the operating circuitry when the supply voltage has fallen below a level that can cause anomalous or unreliable operation. Certain selected transistors are provided with saturation sensors which operate to produce a current when the transistors go into collector saturation. When any of the sensors indicates the onset of saturation, clamping circuitry is energized to provide lock out. In addition, a temperature compensated dummy bandgap circuit is included to sense extremely low supply voltages and provide the lockout function under conditions where a reliable saturation indication might not be available.

Low voltage lockout circuit

A voltage regulator circuit is set forth in which the series pass transistor has its high impedance (collector/drain) electrode connected to the output terminal and a shunt transistor has its low impedance (emitter/source) electrode connected to the output terminal. The circuit is arranged to ensure that the shunt transistor is always conductive so that its low impedance electrode will stabilize the operation of the circuit without requiring any external components. The circuit can be fabricated in either bipolar or CMOS form and a low dropout configuration is employed.

Stabilized low dropout voltage regulator circuit

An integrated circuit is disclosed having a thermal shutdown capability. A single chip bonding pad is coupled to a circuit that will operate the bonding pad at a low potential for normal conditions and will pull it high when a temperature threshold is crossed. Thus, the normally low bonding pad provides a temperature flag. The bonding pad is also coupled to a latch that will hold it high and to a lockout circuit that acts to disable the heat producing chip circuitry. Therefore, when the bonding pad is once driven high the circuits are locked out and will remain out until a start up command is present. This is achieved by either momentarily removing the power supply or by pulling the bonding pad low. Both manual and computer control of the circuit is disclosed.

Integrated circuit thermal limit

An isolation diffusion process monitor is disclosed. A monitor resistor which has one end terminated in an isolation diffusion region is measured during the wafer fabrication process. Its value will be a function of the lateral surface extent of the isolation diffusion.

Growing community of inventors

San Francisco, CA, United States of America

Robert A Pease