Motorola Corporation

Robert A Neidorff

Robert B Jarrett

W Eric Main

Gordon H Allen

An improved input ranging divider and method for an analog to digital converter in which a floating common input line to the A to D comparator is coupled through an R/2R resistive input ladder. A constant reference voltage is applied to the other comparator input. By applying an input voltage to a certain input terminal or terminals of the input ranging divider, while the remaining terminals are either grounded or left floating, a wide range of diverse operating ranges may be made available to an A to D converter while utilizing only a small overall number of inputs.

Input ranging divider and method for an analog to digital converter

A circuit for driving a serial data bus with serial logic data that is supplied to the circuit while buffering the logic data supplying circuit from the data bus. The circuit provides logic output pulses having controlled slew rates wherein the input logic data is not distorted but which inhibits undesired high frequency components associated with the fast rise and fall times of the leading and trailing edges of the input logic data pulses. The circuit comprises an inverting amplifier having capacitive feedback between the output and the inverting input of the amplifier, a buffer amplifier between the output of the inverting amplifier and the output of the circuit, and current switching circuitry for sinking and sourcing currents of equal magnitude at the input of the inverting amplifier depending on the relative magnitude of the input logic data pulses.

Fixed slew rate bus driver circuit

This relates to a circuit for clamping the voltage across first and second terminals (in this case the gate and source electrodes of a power MOSFET) in response to the receipt of a signal indicating a load fault. An input turnaround transistor receives the signal indicative of the fault and generates a current in response thereto which is applied to the base of a switching transistor. When this current exceeds a predetermined value, the switching transistor turns on which in turn causes a buffer circuit including a PNP transistor to turn on. When the buffer circuit turns on, current is drawn through a zener diode which is coupled to the second terminal. Thus, the clamping circuit between the gate and source terminals equals the voltage drop across the zener diode plus that dropped across the buffer circuit plus the saturation voltage of the switching transistor. Resistors are provided in the buffer circuit to provide for a certain amount of adjustment of the clamping voltage.

Clamp circuit

A two terminal monolithic integrated clamp circuit includes first and second circuits coupled between the two input terminals thereof for clamping the voltage appearing across the two terminals to a predetermined voltage. The first circuit is responsive to the voltage level appearing at the first terminal exceeding the voltage level at the second terminal by said predetermined amount for clamping the voltage level thereat while shunting the majority of the current through the clamping circuit to substrate ground of the integrated circuit. The second circuit is responsive to the voltage level appearing at the second terminal exceeding the voltage level at the first terminal by said predetermined amount for clamping the voltage thereat while shunting the majority of the current to substrate ground.

Symmetrical diode clamp

This relates to a comparator circuit for monitoring intelligence on a data bus, which circuit consumes no power until activated by a predetermined voltage on the data bus. An input PNP transistor has a base coupled to the data bus. An emitter resistor and a collector resistor may be scaled to achieve a desired switching threshold. A second PNP transistor has a base coupled to the bus and an emitter coupled to the collector of the first PNP transistor such that the second PNP transistor does not turn on until the first PNP transistor saturates. The collector of the second PNP transistor is coupled to the base of an output NPN transistor and supplies drive thereto when the second PNP transistor is on.

Comparator circuit

This relates to a programmable ring oscillator which comprises a plurality of series coupled gates the output of the last of which is fed back to the input of the first. Bypass means are coupled across the outputs of selected gates so as to in effect increase or decrease the length of the string. In one embodiment, laser trimmable fuses are employed in the bypass networks. In a second embodiment, a data selector under external control is employed.

Programmable ring oscillator

A monolithic integrated temperature compensated voltage reference circuit that includes a thermal source circuit for producing a current at an output thereof having a positive temperature coefficient and an output circuit coupled to the thermal source circuit which is responsive to this current for establishing an output voltage having a substantially zero temperature coefficient associated therewith.

Temperature compensated voltage reference circuit

Two current mirror circuits employing a combination of JFET's and bipolar transistors and a high gain amplifier including one of the mirrors are disclosed. The mirrors each include input and output bipolar transistor with a JFET variable current sink circuit connected across the collector-to-base electrodes of one of the bipolar transistors and a JFET constant current supply is connected to the variable current sink. One of the mirrors further includes a bipolar turn-around circuit connected between the constant current supply and the variable current sink to compensate for otherwise possibly undesirable effects of the base currents of the input and output bipolar transistors.

Current mirror circuits with field effect transistor feedback

A circuit is disclosed for providing multiple output currents having magnitudes which are of a predetermined ratio of the magnitude of an input current. The circuit includes an input transistor and at least two output transistors. The emitters and bases of the input and two output transistors are connected in common with the emitters thereof being connected to a terminal at which is supplied a source of operating potential. The collectors are respectively coupled to individual utilization means. First and second additional transistors are provided having symmetrical structures with the bases thereof being connected to the bases of the output transistors and their emitters connected to the collector of the first output transistor. The collectors of the two output transistors are connected respectively to the collector of the input transistor and the collector of the second output transistor whereby all of any saturation current produced by the first output transistor becoming saturated is equally conducted between the two additional transistors to maintain the ratio of input and output currents.

Current source having saturation protection

A circuit for providing a current having a positive temperature coefficient including a first circuit for producing a first current having substantially a constant temperature coefficient (or a negative temperature coefficient) of a first predetermined value. The first current source is coupled to a current sink circuit which sinks a known value of current from said first circuit, the current sunk by the current sink circuit having a negative temperature coefficient of a second predetermined value. The negative temperature coefficient current of the current sink circuit being greater than the negative temperature coefficient of the current source so that a difference current is provided having a positive temperature coefficient.

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Chandler, AZ, United States of America

Robert A Neidorff