Texas Instruments Corporation

Freescale Semiconductor,inc.

Nxp B.v.

Nxp Usa, Inc.

Other

Robert A McGowan

Gary L Swoboda

Robert N Ehrlich

Douglas E Deao

Leland J Szewerenko

Deborah C Keil

Craig D McLean

Michael Andrew Fischer

Michael Brian Schinzler

Brian Christopher Kahne

Arun Kumar Barman

Amar Nath Deogharia

Kevin C Heuer

Devendra Bahadur Singh

Petru Lauric

Rahul Agrawal

Michael L Olivarez

Nancy J McGowan

Stephen J Benzel

Pradeep Singh

A virtualized controller area network (CAN) system including multiple virtual CAN controllers and a CAN virtual network controller. The CAN virtual network controller includes virtual CAN interfaces, network interfaces, and a configuration controller. Each of the virtual CAN interfaces communicatively links each virtual CAN controller with the network interfaces, which are each configured to communicatively link one or more of virtual CAN controllers into a CAN network. The configuration controller programs any one or more of the network interfaces to communicatively link any one or more of the virtual CAN controllers in each of one or more CAN networks. The configuration controller configures a network interface for virtual communications for implementing a virtual CAN network, or enables a linked physical protocol engine for implementing a physical CAN network. The number of protocol engines needed, if any, may be significantly reduced thereby reducing pin count and silicon area consumption.

Scalable virtualized controller area network system

An SoC with a multiple level resource isolation system including initiator devices that conduct transactions with addressed slave devices via an interconnect, access identifier assignment (AIDA) devices that append an access identifier (AID) including a group identifier (GID) and a domain identifier (DID) to each transaction of a corresponding initiator device, access control (AC) devices that control access to slave devices based on an AID provided with a transaction, a partition manager that programs GIDs into the AIDA and AC devices for assigning slave devices to groups, and group managers that program DIDs into the AIDA devices for each matching GID programmed therein, and that program the AC devices with access rights to one or more DIDs for each slave device assigned to a corresponding group with a matching GID programmed therein.

Multiple level SoC resource allocation and isolation system and method

A system, method, and apparatus are provided for handling communications with external communication channel hardware devices by a processor executing event-based programming code to interface a plurality of virtual machines with the external communication channel hardware devices by providing the processor with an event latch for storing hardware events received from the external communication channel hardware devices, with a timer circuit that generates a sequence of timer interrupt signals, and with a masking circuit that masks the hardware events stored in the event latch with an event mask in response to each timer interrupt signal, where each event mask is associated with a different virtual machine running on the processor such that each virtual machine is allowed to communicate only on a masked subset of the hardware events specified by the event mask to ensure freedom from interference between the plurality of virtual machines when communicating with the external communication channel hardware devices.

Freedom from interference for aggregated communication channel handling using event-based processor extensions

A system comprises a plurality of components, scan chain selection logic coupled to the components, and override selection logic coupled to the scan chain selection logic. The scan chain selection logic selects various of the components to be members of a scan chain under the direction of a host computer. The override selection logic detects a change in the scan chain and, as a result, blocks the entire scan chain from progressing.

Scan path only one-bit scan register when component not selected

Status register between test data I/O of scan port SUT

A method and information processing system provide trace compression for trace messages. In response to a branch of a conditional branch instruction having not been taken or having been taken, a flag of a history buffer is set or cleared. A trace address message is generated in response to a conditional indirect branch instruction being taken, wherein the trace address message includes address information indicating the destination address of the taken branch, and an index value indicating a corresponding flag of the history buffer. In response to a return from interrupt or return from exception instruction, a predicted return address is compared to an actual return address. A trace address message is generated in response to the predicted and actual return addresses not matching. A trace address message is not generated in response to the predicted and actual return addresses matching.

Debug method and device for handling exceptions and interrupts

Debug method and device for providing indexed trace messages

Blocking the effects of scan chain testing upon a change in scan chain topology

A program trace data compression mechanism in which execution of a variable length execution set (VLES) including multiple non-branch conditional instructions are traced in real-time in a manner that allows the instruction execution to be reconstructed completely by correlating the trace data with the traced binary code.

Predicate trace compression

A method and apparatus for an asynchronous multicore common debugging system is described. Debug signals from a plurality of processor cores are synchronized to a common timing domain. Processing completed within the plurality of processor cores during a common timing interval is tracked. A single debugging tool chain is utilized to provide debugging results in response to the tracking the processing completed within the plurality of processor cores during the common timing interval.

System and method for multicore processing

Growing community of inventors

Cedar Park, TX, United States of America

Robert A McGowan