Compaq Computer Corporation, Inc.

Hewlett-packard Development Company, L.p.

Western Atlas International, Inc.

Compaq Information Technologies Group, L.p.

Schlumberger Technology Corporation

Hewlett-packard Company

Robert A Lester

Phillip M Jones

Gary J Piccirillo

Jerome J Johnson

John Edward Larson

Kenneth T Chin

Michael J Collins

John MacLaren

Christian H Post

Jeffery L Galloway

Eric Rose

Ronald Timothy Horan

Gregory N Santos

Clarence K Coffee

Siamak Tavallaei

Patrick Lee Ferguson

Tim W Majni

Anisha Anand

Jeffrey C Stevens

Paul A Santeler

Jeff W Wolford

George D Megason

Robert C Elliott

Brett D Roscoe

Ho M Lai

Benjamin H Clark

Paul B Rawlins

C Kevin Coffee

Dwight D Riley

David R Beard

David J Maguire

Jeffrey S Autor

Christopher C Wanner

James R Edwards

Paul G Junghans

Gregory J Wilkinson

Elizabeth Anne Richard

Lee H Gollwitzer

Dan Fink

Bret D Roscoe

Sompong Paul Olarig

James Robert Birchak

Peter K Lee

Kenneth A Jansen

William J Walker

Maria L Melo

Jens K Ramsey

Mathew G Schmidt

Clarence Coffee

Paul H Vu

Jose Rene Casarsa

George Attali

John D Battles

Donald J Hilliker

Milton E Cram

Robert C Elliot

James Andre

Jim Blocker

Darrell R Haskell

Timoth W Majni

Jeff Stevens

Jean P Masson

Carlos Yansig

Jean-Pierre Hrm Masson

A system includes a mechanism to detect addition of a memory module. In response to the addition of the memory module, a memory test is run to test the new memory module for a defect. If an uncorrectable error is detected, a routine is activated to process the error. Depending on whether the defect occurred in the new memory module or existing memory module(s), different processing is performed.

Handling memory errors in response to adding new memory to a system

A computer system includes a plurality of memory modules that contain semiconductor memory, such as DIMMs. The system includes a host/data controller that utilizes an XOR engine to store data and parity information in a striped fashion on the plurality of memory modules to create a redundant array of industry standard DIMMs (RAID). The host/data controller also interleaves data on a plurality of channels associated with each of the plurality of memory modules. The system implements error interrupt control, ECC error reporting, cartridge error power down procedures in response to command errors, storage of error information in unused segments of each DIMM, hot-pug procedure indicator and remote tagging capabilities of memory cartridges and DIMMs.

Error indication in a raid memory system

A transaction generator generates memory transactions identical to processor memory transactions to initialize, rebuild, and verify memory added or replaced during operation of a computer system configured for RAID memory. The transactions read and rewrite the correct value for replaced memory and write a known good value for added memory. Memory writes are verified by a read after the write transaction. The transaction generator is a state machine. A first counter is used for holding memory addresses of the transactions, automatically incrementing after each transaction. A second counter can throttle the generation of transactions by controlling the incrementation speed of the first counter. Transactions generated by the transaction generator have a transaction identifier, selected from a pool of available transaction identifiers. The transactions can complete out of order.

Transaction generator for initialization, rebuild, and verify of memory

Method and apparatus for improving processor performance. In some embodiments, processing speed may be improved by reusing data stored in a buffer during an initial request by subsequent requests. Assignment of temporary storage buffers in a controller may be made to allow for the potential for reuse of the data. Further, a hot buffer may be designated to allow for reuse of the data stored in the hot buffer. On subsequent requests, data stored in the hot buffer may be sent to a requesting device without re-retrieving the data from memory.

Technique for improving processor performance

A processor-based device having a plurality of memory cartridges secured within a chassis by a lever system. The processor-based device comprises an indication system to indicate memory system operating conditions. Each memory cartridge has a protective assembly to protect memory elements within the memory cartridge when the memory cartridge is removed from the processor-based device. The processor-based device is operable such that at least one memory cartridge may be removed from the processor-based device without affecting operation of the processor-based device.

Removable memory cartridge system for use with a server or other processor-based device

A computer system includes a plurality of memory modules that contain semiconductor memory, such as DIMMs. The system includes a host/data controller that utilizes an XOR engine to store data and parity information in a striped fashion on the plurality of memory modules to create a redundant array of industry standard DIMMs (RAID). The host/data controller also interleaves data on a plurality of channels associated with each of the plurality of memory modules.

Method for supporting multi-level striping of non-homogeneous memory to maximize concurrency

The control logic for a hot-pluggable memory cartridge for use in a redundant memory system. To implement a hot-pluggable memory cartridge in a redundant memory system, control logic to control the sequence of events for powering-up and powering-down a memory cartridge is provided.

Hot replace power control sequence logic

Methods for improving processor performance. Specifically, by reducing some of the latency cycles within a host controller, request processing speed can be improved. One technique for improving processing speed involves initiating a deferred reply transaction before the data is available from a memory controller. A second technique involves anticipating the need to transition from a block next request (BNR) state to a bus priority request (BPRI) state, thereby eliminating the need to wait for a request check to determine if the BPRI state must be implemented.

Method for improving processor performance

A method of adding memory capacity to a computer system. The computer system comprises a redundant memory system including a plurality of memory cartridges. By powering-down a memory cartridge, adding an additional memory module to the memory cartridge, and powering-up the memory cartridge for each memory cartridge in the system, the system can transition from a redundant mode of operation to a non-redundant mode of operation for each power-down, thus allowing the computer system to remain functional during the addition of the memory module. Alternatively, memory cartridges with higher memory capacity than those currently present in the computer system can be used to replace existing memory cartridges in the computer system, using the same techniques.

Hot-upgrade/hot-add memory

A system and technique for correcting data errors in a memory device. More specifically, data errors in a memory device are corrected by scrubbing the corrupted memory device. Generally, a host controller delivers a READ command to a memory controller. The memory controller receives the request and retrieves the data from a memory sub-system. The data is delivered to the host controller. If an error is detected, a scrub command is induced through the memory controller to rewrite the corrected data through the memory sub-system. Once a scrub command is induced, an arbiter schedules the scrub in the queue. Because a significant amount of time can occur before initial read in the scrub write back to the memory, an additional controller may be used to compare all subsequent READ and WRITE commands to those scrubs scheduled in the queue. If a memory location is rewritten with new data prior to scheduled scrub corresponding to the same address location, the controller will cancel the scrub to that particular memory location.

Real-time hardware memory scrubbing

A technique for selecting events associated with a hot-plug operation. More specifically, a programmable configuration register may be used to provide a mechanism for periodically scheduling requests associated with a hot-plug operation, such as initialization, rebuild, and verify requests. An arbiter is provided to facilitate an ordered access to a memory system. A user can select a periodic interval such that hot-plug requests are periodically executed during the execution of normal requests through the arbiter. The user-selectable interval may be dependent on the specific application of the system and the importance of operating in a redundant mode.

Rebuild bus utilization

Method for supporting multi-level stripping of non-homogeneous memory to maximize concurrency

A computer system includes a plurality of memory modules that contain semiconductor memory, such as DIMMs. The system includes a host/data controller that utilizes an XOR engine to store data and parity information in a striped fashion on the plurality of memory modules to create a redundant array of industry standard DIMMs (RAID). The system supports DIMMs having X4 and X8 configurations. The system also transitions between various states, including a redundant state and a non-redundant state, to facilitate &ldquo;hot-plug&rdquo; capabilities utilizing its removable memory cartridges.

Raid memory

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Houston, TX, United States of America

Robert A Lester