Zenith Data Systems Corporation

Packard Bell Nec

Nec Corporation

Robert A Kohtz

Lloyd W Gauthier

David J DeLisle

Mark D Nicol

Saifuddin T Fakhruddin

David T DeRoo

Michael P Krau

Richard D Ball

Clark L Buxton

Jimmy D Smith

Robert R Turnbull

Peter A Ojeda

Mark J Foster

David J Delisle

Eric D Fuhs

Wayne L Griffin

Saifee Fakhruddin

Saifee Fakruddin

Jeff Schindler

Steve L Belt

A multiprocessing computer system and method providing multiplexed address and data paths from multiple CPUs to a single storage device. These paths are controlled by an arbitration circuit which allows one CPU to always have the highest priority. The primary CPU may or may not be the highest priority CPU in the arbitration scheme. The arbitration circuit is combined with a controlling mechanism which interfaces to the memory device. This controller operates at a clock rate fast enough to allow the highest priority CPU to access the memory at it's highest data rate and, yet, guarantees a maximum idle period for the lower priority CPU to wait for it's interleaved memory access to complete. A single memory device provides cost and space savings. A controller is responsive to these processors to multiplex their information signals for selectively conveying information present at their address and data ports. A common memory device is addressable by the processors, and responsive to the controller to share addressing of the common memory device.

Multiprocessor system for enabling shared access to a memory

An interface between the host CPU and the programmably memory, providing an address, data and read/write control signals to create a non-volatile sector within the programmable memory. In an embodiment when the system reset is de-asserted immediately after power-on, the size of the protected EEPROM area is sensed on special strapping option pins and automatically configures the non-volatile sector. This allows the size of the protected area to be changed on the manufacturing line as needed for different applications. Once configured to protect a specific size and location in the non-volatile memory, the invention prevents the write control signal to the memory to be asserted when the address of the data access requested by the CPU is in the protected area of the memory. This has the effect of preventing modification of the protected area by a sector modification algorithm.

Protected address range in an electrically erasable programmable read

A computer system employs a process on warm boot which obviates the need to copy code in non-volatile memory to volatile memory; a normal function in a warm boot process. The computer system checks a warm boot flag which indicates that the code was previously copied on cold boot. By avoiding copying this already copied code and executing directly from the volatile memory considerable time is saved. Since BIOS code is typically on the order of 10K bytes, elimination of the necessity to rewrite BIOS and vectoring directly to BIOS image file in RAM saves on the order of ten thousand clock cycles.

Method for warm boot from reset

In the present invention, a single EEPROM is used to store firmware for the CPU, firmware for the SCP and the system password and other critical system data. Hardware protection is provided that prevents the CPU from accessing the portion of the EEPROM that contains the password or other critical systems data.

Method to store privileged data within the primary CPU memory space

The invention provides for a CPU in a digital system to control the location of the code being executed by one or more peripheral CPUs when all CPUs share a common memory. This allows the CPU to allocate convenient (e.g., unused) blocks of its address space for the code for the peripheral CPU(s). Additionally, for digital systems in which the peripheral CPU(s) cannot address the full range of the address space of the shared memory that is available to the CPU, the CPU can control the relocation of the block of code for the peripheral CPU(s) (i.e., provide a code paging system).

Apparatus to allow a CPU to control the relocation of code blocks for

The invention provides a simple I/O port which can be used to support a variety of system functions such as a revision, configuration or identification register. This port is provided with a means to be programmable once, upon system power-up so that changes to the port contents are possible, but only under controlled conditions. Once the register has been programmed, it will no longer respond to writes.

Write inhibited registers

A relatively fast system control processor, such as an Intel 8051, is substituted for an Intel 8042 microprocessor in a PC/AT type compatible personal computer. In one embodiment of the invention, a System Control Processor Interface (SCPI) is provided between the central processing unit (CPU) and the system control processor (SCP) to maintain compatibility with the PC/AT bus. The combination of the faster SCP and the SCPI interface improves the overall system performance. Control circuitry is also provided for setting the A20 signal relatively quickly to allow memory access above one megabyte. In an alternate embodiment of the invention, a Mouse Keyboard Interface (MKI) is provided. The MKI provides even quicker switching of the Gate A20 signal by eliminating the need to interrupt the SCP. The MKI also provides support for a type PS/2 mouse.

Hardware based interface for emulation of a standard system control

An enhanced parallel port interface increases the bandwidth of a standard parallel port connector while at the same time maintaining backward compatibility with a standard parallel port interface. In order to increase the data transfer rate, the software overhead is substantially reduced by hardware generated signals. As such, the desirability of using a parallel port bus expansion is greatly increased.

Control system for a multiple mode standard parallel port for a personal

An apparatus and method for tracking and interception of instructions as they are presented to the memory, selectively passing harmless data to the device and disallowing the sequences which instruct the device to perform harmful functions, such as self-erase. A software trap is provided to be transparent to the operation of the device and the host system, imposing no harmful timing delays or software overhead. Accordingly, the invention allows the use of standard electrically erasable read-only memories in an application which requires that the device be protected from global erasure. A hardware front end intercepts the software command which is used to globally erase the device. The apparatus receives address signals from the computer system corresponding to the protected peripheral device, receives data signals from the computer system to the protected peripheral device, tracks a predetermined sequence of address and address signals, substitutes at least one of the data signals received with a replacement data signal, and sends a replacement data signal.

Method to prevent data loss in an electrically erasable read only memory

A method and circuit for relatively accurately measuring the die temperature of an IC, such as a microprocessor, by sensing one or more internal circuit elements which have an electrical parameter which varies as a function of temperature, such as an input protection diode. By sensing the one or more circuit elements which have an electrical parameter that is temperature dependent, the method provides a relatively more accurate measurement of the die temperature than measuring the outside temperature of the IC package. In addition, a control circuit is provided for cooling the IC during excessive temperature conditions by slowing down the clock frequency of the IC until the die temperature is within the temperature limit in order to optimize the utility of the IC during excessive temperature conditions.

Method and control circuit for measuring the temperature of an

A computer disk drive control adapts the rate of data transfer between a disk drive and a CPU to correspond to one of three industry standard transfer rates. The timing of disk controller signals is provided for by a two phase state machine that receives a signal representative of a selected data transfer rate and generates disk controller signals of the appropriate frequency and configuration. Such disk controller signals cause a disk controller to effect data transfer at the selected rate. In a preferred embodiment, the two phase state machine is driven by two opposite phases of a single 24 MHz clock.

Control system and method for multiple rate disk drive data transfer

Hardware based interface for mode switching to access memory above one

A computer bus interface suited to connecting an expansion bus to a computer's internal bus. The interface is capable of selecting and deselecting any devices coupled to the expansion bus by enabling and disabling buffers which intercept signals between the expansion bus and the internal bus.

External expansion bus interface

An improved means and method for expanded memory system access and control is disclosed. A logic array in the expanded memory control circuitry which accesses and controls up to two separate expansion boards through the use of static random access memory as register circuits and octal buffers for addressing. The control and access method implemented through a state machine in the logic array provides the operation of the improved expanded memory system to control additional expansion boards and to access the appropriate memory locations.

Growing community of inventors

St. Joseph, MI, United States of America

Robert A Kohtz