Gte Automatic Electric Laboratories Incorporated

Gte Automatic Electric Incorporated

Robert A Karchevski

Incoming data in binary form is retimed, and under control of a framing clock, a first counter clocks in four bits in the first stage of a preview store; and a second counter clocks in eight bits, four bits in each of the second and third stage of the preview store. The first bit in each instance is the framing bit for the next previous frame location and the second next previous frame location so long as an in-frame condition exists, and the frame control is in synchronism with the framing bits contained in the incoming data. The current data bit is compared with the bits appearing at the output of the first and second stages of the preview store to determine if the three bits comprise a valid framing sequence for a non-winking framing sequence in which any combination of the following frame bit indications may occur-F1 F0 F0 F1-where the number following the F indicates the state of the framing bit. If they do, the counters shift the four and eight bits as noted above to establish the condition necessary for comparison with the next incoming framing bit. Although the current data bit will constantly change with the character of the data, false error indications are prevented by use of a coincident circuit with the comparator output and a delayed frame clock signal. If framing errors occur, these are passed through the coincident circuit to an error density detector. If the error rate exceeds a predetermined value, the state of the output signal from the error density detector is changed. The counters respond to this condition by stepping the stored bits through the registers of the preview store one bit at a time and, of course, a comparison is made at each step and, if a valid sequence is detected, the output of the detector is applied to the counter to halt the stepping sequence. Then the counters read in the four and eight bits of data which data is then held for comparison at the next framing bit location. If the in-frame condition obtains, this sequence is repeated at each frame bit occurrence. If not, the search mode will again exist and the stepping sequence will be repeated.

Frame detection and synchronization system for high speed digital

One or a burst of error signals from an error detector are applied to one input of a latch. The first error received during a 'window' forces the latch to a set position, and a subsequent enabling pulse reads the error occurrence into the count up input of an up-down counter. Following the enable pulse, the latch is reset. If one or more errors occur during the subsequent window period, another error occurrence is read into the count up input. Otherwise, the occurrence of the enable pulse reads the absence of an error into the down count input of said up-down counter. On a full count, an output latch circuit is set by an output signal from the counter. The latch is not reset until a zero count is obtained in the up-down counter. Overflow and underflow are prohibited by circuits external to the up-down counter.

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San Mateo, CA, United States of America

Robert A Karchevski