International Business Machines Corporation

Robert A Henle

James L Walsh

Richard R Konian

Joseph R Cavaliere

Alfred H Johnson

Narasipur G Anantha

Irving T Ho

A semiconductor chip is so designed that the signal and power terminals are brought to one edge of the integrated circuit chip. The integrated circuit chip is then mounted vertically on a substrate which provides signal interconnection and power distribution to the integrated circuit chips as well as a thermal path for conducting heat away from the chips. The electrical connection from the semiconductor chip to the substrate may be by solder reflow or thermal compression bonding techniques. The package is particularly advantageous for memory integrated circuit chips. The vertical integrated circuit chips may alternatively be carried by a tape carrier which is formed into a convoluted form with all integrated circuit chips positioned substantially vertically thereon. This carrier is then bonded electrically and physically to a substrate in areas associated with the integrated circuit chips so that when the substrate is substantially horizontal the integrated circuit chips are substantially vertical in relation thereto. In this alternative, electrical connections may be made to more than one edges of the integrated circuit chips.

Vertical semiconductor integrated circuit chip packaging

A high speed, unity gain, emitter follower OR circuit is disclosed including first and second pairs of emitter-connected complementary bipolar transistors with the bases of the NPN transistors being connected together and the bases of the PNP transistors being connected commonly to an input line. One of the NPN transistors id diode-connected (base to collector). The emitter of the other NPN transistor is connected to an output terminal. The input line is connected to the emitters of a pair of OR input NPN transistors and to a first current source. A second current source is coupled to the diode-connected NPN transistor.

Unity gain emitter follower bridge circuit

A complementary bipolar transistor circuit characterized by the same output impedance for positive and negative input voltage transitions, only a single collector path delay between input and output for both senses of input voltage transitions and very low standby power consumption. Provision is made for simultaneously actuating an emitter follower series-connected first pair of complementary transistors with signals having voltage swings which are only a fraction of the V.sub.be necessary to forward bias each base-emitter diode of the first pair of transistors. The actuation is accomplished using a second pair of complementary transistors having collector electrodes connected to respective bases of the first pair of transistors of similar kind. One of the remaining electrodes of each of the second pair of transistors are connected to each other. In a driver circuit species of the invention, the bases of the second pair of transistors are connected to each other and receive the input signal. In a logic circuit species of the invention, the emitter of one of the second pair of transistors is connected to the base of the other of the second pair of transistors. NOR logic is performed by connecting additional transistors in parallel with said one of the second pair of transistors, the bases of the additional transistors receiving respective logic input signals. The output from the driver circuit as well as from the logic circuit is derived from the commonly connected emitters of the first pair of transistors. The first pair of transistors conduct only during the transitions of the input signals.

Complementary transistor inverting emitter follower circuit

A small variable resistor is used as a precision terminating resistor in an integrated circuit interconnection structure. The structure involves the use of a driver circuit connected to and driving a plurality of loads which are connected to a transmission line. The transmission line is terminated by the precision variable terminating resistor. The last load in the series of loads is located in the integrated circuit chip which has the variable terminating resistor. The absolute value of the variable resistor is difficult to control. The absolute value of any conventional integrated resistor is hard to control in manufacturing. However, by making the value of the resistance proportional to a voltage which itself is proportional to a deviation from a reference voltage, it is possible to obtain a much more precise value of resistance.

Integrated circuit interconnection structure having precision

An intermediate driver circuit comprising at least five stages which are cascaded between a signal driver, such as a logic circuit on an LSI chip, and a high capacity load driver, such as a driver for long off chip interconnection lines, wherein the total delay in the signal source caused by great disparity between the capacitance of the signal driver and the load driver is minimized. The delay is minimized by use of a cascaded series of n-intermediate drivers where n=1nM, ##EQU1## AND WHERE THE CAPACITANCE OF ANY INTERMEDIATE STAGE IS C.sub.P =.sqroot.C.sub.(P.sub.-1) .sup.. C.sub.(P.sub.+1). Use of these parameters in the design of intermediate stages, each having a capacitance designed in accordance with the foregoing equations has been found to be useful in connection with amplifiers having five or more intermediate stages, and wherein the ratio of capacitance of the load circuit to the capacitance of the driver circuit is greater than about one hundred to one. The utility of these design parameters in instances where the ratio of capacitance is greater than a thousand to one, and the number of intermediate stages is ten or greater is particularly apparent.

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Clinton Corners, NY, United States of America

Robert A Henle