Texas Instruments Corporation

Ams Ag

Robert A Helmick

Kevin M Ovens

Rohit L Bhuva

Walter C Bonneau, Jr

Allen Y Chen

Robert L Gruebel

A photodiode array is disclosed and comprises a first photodiode comprising a first set of spatially separate and electrically interconnected photodiode segments. A second photodiode comprises a second set of spatially separate and electrically interconnected photodiode segments. A first group of photodiode segments comprises photodiode segments from the first and/or second set of photodiode segments. The photodiode segments from the first group of photodiode segments are radially arranged around a common center of symmetry in a common first distance with respect to the common center of symmetry. A second group of photodiode segments comprises photodiode segments from the first and/or second set of photodiode segments. Photodiode segments from the second group of photodiode segments are radially arranged around the common center of symmetry in a second common distance with respect to the common center of symmetry, wherein the first distance is different from the second distance. Each photodiode has an area matched counterpart photodiode forming a matched pair of photodiodes. The matched counterpart photodiodes comprise a matched set of spatially separate and electrically interconnected photodiode segments. Each group of photodiode segments comprises the corresponding matched set of photodiode segments.

Photodiode array

In one aspect of the present invention, a converter is provided comprising a capacitive coupling arranged to receive said input signal to be converter, and a conversion circuitry coupled to the capacitive coupling to produce the converted output signal. A biasing circuit is further arranged to facilitate a fast transition in the converted output signal in response to an active transition in the input signal.

Apparatus and method for ECL-like signal to CMOS signal conversion

A circuit (90) converts a true ECL signal to a true TTL signal. The circuit includes a differential circuit (180) that receives an ECL signal having high and low values. The differential circuit produces a differential signal therefrom that has a high value in response to one of the high and low values of the true ECL signal, and a low value in response to the other of the high and low values of the true ECL signal. A first translator circuit (36, 64) has an input (32) coupled to the differential circuit (180). The first translator circuit (36, 64) transmits a true low TTL output (56) signal having a voltage level referenced to the voltage level of a TTL low supply voltage in response to receiving a high value of the differential signal. A second translator circuit (46, 52) has an input (38) and is coupled to a TTL high supply voltage and the output (56). An input signal appearing on the input (38) of the second translator circuit has a voltage level related to the voltage level of the differential signal (32). The second translator circuit (46, 52) transmits a high TTL output signal having a voltage level referenced to the voltage level of the TTL high supply voltage in response to the differential signal (32) being at a low value.

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Allen, TX, United States of America

Robert A Helmick