Digital Equipment Corporation

Robert A Giggi

Richard Franklin Lary

Daniel T Sullivan

Jega A Arulpragasam

A multiprocessor data processing system, the processors (30) and input/output devices (32) of which share a common control unit (CCU 10) that includes a write-through cache memory (20), a memory management circuit (22) and an address translation circuit (24). The data processing system further includes random access memory (28) and a secondary storage facility (40, 42, 68, 70). The processors (30) and the input/output devices (32) use the memory management circuit (22), the address translation circuit (24) and the cache memory (20) in an ordered pipelined sequence. When a read command 'misses' the cache memory (20), the CCU accesses the memory modules (28) for allocating its cache memory (20) and for returning read data to the processors (30) or input/output devices (32). The CCU also includes a duplicate tag store (67) that maintains a copy of the cache memory address tag store (20A) thereby to enable the CCU to update its cache memory when data is written into a memory location that is to be maintained in the cache memory.

Cached multiprocessor system with pipeline timing

A cached multiprocessor system operates in an ordered pipeline timing sequence in which the time slot for use of the cache is made long enough to permit only one cache access. Further, the time slot for data transfers to and from the processors succeeds the time slot for accessing the cache. The sequence is optimized for transactions that require only one cache access, e.g., read operations that hit the cache. Transactions that require two cache accesses must complete the second cache access during a later available pipeline sequence. A processor indexed random access memory specifies when any given processor has a write operation outstanding for a location in the cache. This prevents the processor from reading the location before the write operation is completed.

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Merrimac, NH, United States of America

Robert A Giggi