Intel Corporation

Robert A Gasser

Timothy L Deeter

Shi-Ning Yang

Melton C Bost

Gilroy J Vandentop

Sunit Tyagi

Mohsen Alavi

Payman Aminzadeh

A method of forming a guard wall for a semiconductor die is described. A dielectric layer is deposited over a semiconductor substrate. The dielectric layer is patterned to form a guard wall opening extending through the dielectric layer. The guard wall opening lies adjacent to an electrically active region of the die. The guard wall opening has a pattern without any straight line segments greater than about 10 .mu.m long. A first layer is deposited over the substrate and etched to form a first layer sidewall spacer along a side of the guard wall opening. A second layer is deposited within the guard wall opening to form the guard wall.

Guard wall to reduce delamination effects within a semiconductor die

A monitoring device to monitor process induced charge employing a single layer of polysilicon forming a floating gate. The device comprises two capacitors, one for charging and the other for discharging a floating gate of an n-channel transistor. Embodiments which permit the monitoring of positive charge, negative charge and both positive and negative charge are described. The device is reusable and lends itself to in-line monitoring as opposed to some prior art devices used for end-of-line monitoring.

Single poly devices for monitoring the level and polarity of process

Method of forming a guard wall to reduce delamination effects

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Tigard, OR, United States of America

Robert A Gasser