Rosestreet Labs, LLC

Other

Flipchip International LLC

Beezerbug Incorporated

Park Electrochemical Corporation

Robert A Forcier

Paul Brantner

Marsha M Forcier

Wladyslaw Walukiewicz

Jeffrey D Flammer

Douglas M Scott

Jordan Lane Wahl

Tayfun Ilercil

Sukianto Rusli

Edwin J Adlam

Jerome S Sallo

An ultraviolet light sensor and method of manufacturing thereof are disclosed. The ultraviolet light sensor includes Group-III Nitride layers adjacent to a silicon wafer with one of the layers at least partially exposed such that a surface thereof can receive UV light to be detected. The Group-III Nitride layers include a p-type layer and an n-type layer, with p/n junctions therebetween forming at least one diode. Conductive contacts are arranged to conduct electrical current through the sensor as a function of ultraviolet light received at the outer Group-III Nitride layer. The Group-III Nitride layers may be formed from, e.g., GaN, InGaN, AlGaN, or InAlN. The sensor may include a buffer layer between one of the Group-III Nitride layers and the silicon wafer. By utilizing silicon as the substrate on which the UV sensor diode is formed, a UV sensor can be produced that is small, efficient, cost-effective, and compatible with other semiconductor circuits and processes. The sensor may be configured to be sensitive to a specific subtype or subband of ultraviolet radiation to be detected by selecting a specific composition of said Group-III Nitride layers.

Nitride UV light sensors on silicon substrates

A semiconductor integrated circuit has one or more integral nitride-type sensors. In one embodiment, an integral nitride-type sensor and a coplanar supplemental circuit are formed from a common silicon substrate base. In another embodiment, an integral nitride-type sensor and a supplemental circuit are integrated in a vertical orientation.

Structure and method for forming integral nitride light sensors on silicon substrates

Disclosed is a package that includes a wafer substrate and a metal stack seed layer. The metal stack seed layer includes a titanium thin film outer layer. A resist layer is provided in contact with the titanium thin film outer layer of the metal stack seed layer, the resist layer forming circuitry. A method for manufacturing a package is further disclosed. A metal stack seed layer having a titanium thin film outer layer is formed. A resist layer is formed so as to be in contact with the titanium thin film outer layer of the metal stack seed layer, and circuitry is formed from the resist layer.

Thin film structure for high density inductors and redistribution in wafer level packaging

A transceiver preferably embedded within a wearable security watch, PDA, or other device which achieves a variety of wireless ultrasonic and/or radio-frequency based functions, including digital identification and proximity and sensation monitoring of assets, individuals, pets, and the like. The portable or wearable device realizes these functions by periodically polling and receiving information tags within the transmitting distance of the device. The invention can help reduce the likelihood of the theft, loss, or misplacement by detecting that a tag associated with or attached to an entity has left an individual's proximity and sounding an alarm. The device can also assist individuals with sensory impairments, including persons who are deaf, diabetic, and the like, by detecting a tagged entity as it enters the space around an individual, or by detecting environmental stimuli, such as excessive heat in an individual's proximity or vital sign changes, and sounding an alarm.

Ultrasonic transmitter and receiver systems and products using the same

A rigid-flex circuit board system that can be manufactured using less expensive and more reliable rigid circuit board methods and equipment, and can maintain rigidity and dimensional stability until the time when it is first desired to flex.

Rigid-flex circuit board system

A build-up structure for chip to chip interconnects and System-In-Package utilizing multi-angle vias for electrical and optical routing or bussing of electronic information and controlled CTE dielectrics including mesocomposites to achieve optimum electrical and optical performance of monolithic structures. Die, multiple die, Microelectromechanical Machines (MEMs) and/or other active or passive components such as transducers or capacitors can be accurately positioned on a substrate such as a copper heatsink and multi-angle stud bumps can be placed on the active sites of the components. A first dielectric layer is preferably placed on the components, thereby embedding the components in the structure. Through various processes of photolithography, laser machining, soft lithography or anisotropic conductive film bonding, escape routing and circuitry is formed on the first metal layer. Additional dielectric layers and metal circuitry are formed utilizing multi-angle vias to form escape routing from tight pitch bond pads on the die to other active and passive components. Multi-angle vias can carry electrical or optical information in the form of digital or analog electromagnetic current, or in the form of visible or non-visible optical bussing and interconnections.

Build-up structures with multi-angle vias for Chip to Chip interconnects and optical bussing

Build-up structures with multi-angle vias for chip to chip interconnects and optical bussing

The present invention relates to a bond enhancement process for promoting strong, stable adhesive bonds between surfaces of copper foil and adjacent resin impregnated substrates or superimposed metallic sublayers. According to the process of the invention, a black oxide-coated copper surface is treated with an aqueous reducing solution containing sodium metabisulfite and sodium sulfide to convert the black oxide coating to a roughened metallic copper coating. The roughened metallic copper-coated surface is then passivated and laminated to a resin impregnated substrate. The bond enhancement process is especially useful in multilayer printed circuit fabrication and in the treatment of copper circuit lines and areas which are disconnected from each other, that is, which do not have electrically conductive continuity. Inner-layer laminates prepared according to the process of the invention are not susceptible to pink-ring formation, exhibit excellent resistance to chemical attack at drilled holes and sheared edges and are stable under thermal and mechanical stresses.

Method for making multi-layer circuit boards

A seat cushion for prolonged sitting, having a thigh cushion coupled to and spaced apart from a back cushion. A seat well is defined between the thigh cushion and the back cushion to remove pressure from the buttocks region. Coupling members couple the thigh cushion and the back cushion, and extend therebetween on either side of the seat well.

Lumbar supporting seat cushion

A seat cushion for prolonged sitting, having a thigh cushion coupled to and spaced apart from a back cushion. A seat well is defined between the thigh cushion and the back cushion to remove pressure from the buttocks region. Coupling members couple the thigh cushion and the back cushion, and extend there between on either side of the seat well.

Growing community of inventors

Mesa, AZ, United States of America

Robert A Forcier