Storage Technology Partners

Robert A Feretich

Laurence H Cooke

Richard F Boyle

A scannable asynchronous/synchronous CMOS latch circuit that includes a first, second, and third latch element, an asynchronous latch section, and a clock control section. When operated as a synchronous latch, the first latch element operates as the 'master' portion and the second latch element acts as the 'slave' portion of a master/slave latch. The clock control circuit enables the clock signals to control the synchronous operation of the master/slave latch. When operated as an asynchronous latch, the clock control circuit disables the clock. The output of the asynchronous latch section is connected to the input of the first latch element. An asynchronous signal appearing on one of the inputs of the asynchronous latch section passes through the first and second latch elements and is applied to another input of the asynchronous latch section, causing it to be latched, or held. Separate outputs are provided for the asynchronous latch and the synchronous latch. When scanning occurs, the second and third latch elements act as a shift register stage. The second latch element acts as the master while the third latch element acts and the slave of a master/slave latch. The contents of the asynchronous latch can be latched in the slave section of the synchronous latch for scanning. Shift-in data is coupled to the master, then transferred to the slave, where it appears on the shift-out output, by appropriate clock signals.

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Santa Clara County, CA, United States of America

Robert A Feretich