Analog Devices,inc.

Robert A Duris

Douglas W Babcock

Bruce A Hecht

A Paul Brokaw

Lawrence M DeVito

Alex Gusinov

Scott A Wurcer

Edward B Hilton

Stephan Goldstein

Lewis W Counts

Warren Hambly

A passive matching network is connected to an input/output line for an automatic test equipment drive channel to compensate for capacitances associated with a receiver circuit connected to the line, and also an optional current-mode driver circuit. The matching circuit preferably comprises a T-coil circuit that can include a bridging capacitor; separate T-coil circuits can be provided to separately compensate for receiver circuit and current-mode driver circuit capacitances. The driver and receiver circuits can be implemented on a common layer of an integrated circuit, with the T-coil windings implemented in a separate layer of the same integrated circuit that is spaced from the common layer by at least one dielectric layer.

T-coil apparatus and method for compensating capacitance

Automatic test equipment pin channel with T-coil compensation

Driver circuits and methods for operating driver circuits in automatic test equipment are provided. The driver circuit includes an output circuit operable in a dynamic mode and in a termination mode, and a mode control circuit for supplying a first current to the output circuit in the dynamic mode and for supplying a second current to the output circuit in the termination mode in response to a mode select signal. The mode control circuit may include a current multiplier and a switching circuit for switching a control current supplied to the current multiplier. In one example, the slew current supplied to the output circuit is controlled in response to the mode select signal.

Driver circuit with low power termination mode

A clamp for use with a circuit (having an output for delivering an output voltage) forms a voltage boundary for the output voltage based upon a clamp voltage. To that end, the clamp includes a clamp input for receiving the clamp voltage, a clamp transistor in communication with the clamp input, and a control transistor in communication with the output. The clamp also includes a driving source for driving at least one of the clamp and control transistors based upon the voltage at the clamp input and the voltage at the output. The output is clamped at a voltage within the voltage boundary of the clamp voltage after the clamp transistor begins being driven by the driving source.

Programmable clamp for output circuit

A parasitic capacitance cancellation circuit for a direct bonded silicon-on-insulator integrated circuit includes one or more transistors fabricated silicon-on-insulator; a silicon substrate region outside the transistor(s) having a parasitic capacitance to be cancelled; a bootstrap terminal connected to the region outside the transistor(s); and a unity gain buffer responsive to the output of the transistor(s) and having its output connected to the bootstrap terminals for providing a voltage to the region outside the transistor(s) which follows the voltage developed on the parasitic capacitance and nullifies the parasitic capacitance.

Parasitic capacitance cancellation circuit

A circuit for varying the temperature of a first bipolar transistor in order to thermally compensate for self-heating effects of an associated device in a common signal path with the first transistor, the first transistor being configured within an isolated collector region. The circuit includes a second bipolar transistor provided within the isolated collector region and thermally coupled to the first transistor, the second transistor operable for providing heat to the first transistor to alter the temperature to a predetermined level, thus changing the operational voltage characteristics of the first transistor so as to minimize shifts in offset voltage.

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Hubbardston, MA, United States of America

Robert A Duris