Apple Inc.

Silicon Graphics, Incorporated

Nintendo Co., Ltd.

Ati Technologies Inc.

Graphics Properties Holdings, Inc.

Graphic Properties Holdings, Inc.

Robert A Drebin

Patrick Y Law

Christopher J Migdal

Keith Alan Cox

James S Ismail

John Stephen Montrym

Mark M Leather

Timothy J Van Hook

Mark S Peercy

David L Dignam

John Milligan Airey

James Han Wang

Gregory C Buchner

David S Wang

Danny Loh

Danny D Loh

Matthew Komsthoeft

Terence M Potter

James S Blomgren

Howard H Cheng

Mark Stefan Grossman

Michael Timothy Jones

Robert J Moore

Yoshitaka Yasumoto

Kurt Barton Akeley

Anthony P DeLaurier

James L Foran

Eric Demers

Timothy A Olson

Wade K Smith

Jon A Loschke

Martin Hollis

W Fritz Kruger

David (Chi-Shung) Wang

Douglas C Youngwith

James Wang

Eric c/o Ati Technologies Systems Corp Demers

In one embodiment, a system includes power management control that controls a duty cycle of a processor to manage power. The duty cycle may be the amount of time that the processor is powered on as a percentage of the total time. By frequently powering up and powering down the processor during a period of time, the power consumption of the processor may be controlled while providing the perception that the processor is continuously available. For example, the processor may be a graphics processing unit (GPU), and the period of time over which the duty cycle is managed may be a frame to be displayed on the display screen viewed by a user of the system.

Power management for a graphics processing unit or other circuit

Techniques and structures relating to virtual graphics processing units (VGPUs) are disclosed. A VGPU may appear to software as an independent hardware GPU. However, two or more VGPUs can be implemented on the same GPU through the use of control structures and by duplicating some (but not all) hardware elements of the GPU. For example, additional registers and storage space may be added in a GPU supporting multiple VGPUs. Different execution priorities may be set for tasks and threads that correspond to the different supported VGPUs. Memory address space for the VGPUs may also be managed, including use of virtual address space for different VGPUs. Halting and resuming execution of different VGPUs allows for fine-grained execution control in various embodiments.

Graphical processing unit (GPU) implementing a plurality of virtual GPUs

Techniques are disclosed relating to handling page faults created by a processor unit. In some embodiments, such techniques may be used within the context of graphics processor units (GPUs) to reduce the chances that a page fault will result in a GPU-pipeline stall. In one embodiment, a processor includes a graphics processor pipeline and a memory management unit. The graphics processor pipeline includes a plurality of pipeline stages. The memory management unit is configured to determine that a first data request from a first of the plurality of pipeline stages causes a page fault, and to service requests from one or more others of the plurality of pipeline stages while the page fault is being serviced.

Non-blocking memory management unit

A system and method for efficiently accessing operands in a datapath. An apparatus includes a data operand register file and an execution pipeline with multiple stages. In addition, the apparatus includes a result bypass cache configured to store data results conveyed by at least the final stage of the execution pipeline stage. Control logic is included which is configured to determine whether source operands for an instruction entering the pipeline are available in the last stage of the pipeline or in the result bypass cache. If the source operands are available in the last stage of the pipeline or the result bypass cache, they may be obtained from one of those locations rather than reading from the register file. If the source operands are not available from the last stage or the result bypass cache, then they may be obtained from the data operand register file.

Result bypass cache

A floating point rasterization and frame buffer in a computer system graphics program. The rasterization, fog, lighting, texturing, blending, and antialiasing processes operate on floating point values. In one embodiment, a 16-bit floating point format consisting of one sign bit, ten mantissa bits, and five exponent bits (s10e5), is used to optimize the range and precision afforded by the 16 available bits of information. In other embodiments, the floating point format can be defined in the manner preferred in order to achieve a desired range and precision of the data stored in the frame buffer. The final floating point values corresponding to pixel attributes are stored in a frame buffer and eventually read and drawn for display. The graphics program can operate directly on the data in the frame buffer without losing any of the desired range and precision of the data.

Floating point computer system with fog

Display system having floating point rasterization and floating point framebuffering

The present invention provides for a method of and apparatus for compressing and uncompressing image data. According to one embodiment of the present invention, the method of compressing a color cell comprises the steps of: defining at least four luminance levels of the color cell; generating a bitmask for the color cell, the bitmask having a plurality of entries each corresponding to a respective one of the pixels, each of the entries for storing data identifying one of the luminance levels associated with a corresponding one of the pixels; calculating a first average color of pixels associated with a first one of the luminance levels; calculating a second average color of pixels associated with a second one of the luminance levels; and storing the bitmask in association with the first average color and the second average color. In one embodiment, the color cell includes a matrix of 4&#xd7;4 pixels, the bitmask includes 32-bits and each of the color values includes 16-bits such that a compression rate of 4-bits per pixel is achieved. The present invention is particularly applicable to compress texture data such that the texture data can be more efficiently cached and moved during texture mapping. In that embodiment, the present invention can also support the compression of luminance, intensity and alpha textures.

Method of and apparatus for compressing and uncompressing image data

A method and apparatus for fragment processing in a virtual memory system are described. Embodiments of the invention include a coprocessor comprising a virtual memory system for accessing a physical memory. Page table logic and fragment processing logic scan a page table having a fixed, relatively small page size. The page table is broken into fragments made up of pages that are contiguous in physical address space and logical address space and have similar attributes. Fragments in logical address space begin on known boundaries such that the boundary indicates both a starting address of a fragment and the size of the fragment. Corresponding fragments in physical address space can begin anywhere, thus making the process transparent to physical memory. A fragment field in a page table entry conveys both fragment size and boundary information.

Method and apparatus for fragment processing in a virtual memory system

Growing community of inventors

Palo Alto, CA, United States of America

Robert A Drebin