Metheus Corporation

Tektronix, Inc.

Robert A Bruce

Albert Xthona

Dan Moss

A method and apparatus for generating both a true color and fast pseudo color video signals includes the combination of first and second commercially available RAMDACs. Parallel video data representing the red, blue, and green color components of one or more pixels is provided on a video bus to the inputs of the first and second RAMDACs. A first data portion of the parallel video data is presented to the input of the first RAMDAC, which can represent either a single pixel in the fast pseudo color mode or the most significant pixel data. A second data portion of the parallel video data is presented to the input of the second RAMDAC, which can represent either another single pixel in the fast pseudo color mode or the least significant pixel data. The outputs of the two RAMDACs are combined to provide true color video signals in a first RAM programming mode, and the respective outputs of the two RAMDACs are multiplexed to provide fast pseudo color video signals in a second RAM programing mode.

High speed RAMDAC with reconfigurable color palette

A raster graphic refresh memory architecture offering increased access speed. The memory takes advantage of the 'page mode' of operation of dynamic random-access memory integrated circuit devices which require two separate device addresses for random access to a storage location therein but permit in 'page mode' a first address corresponding to a set of storage locations to be maintained while changing the second address for more rapid access. The memory is organized so that a portion of the second device address is allocated to the least significant bits of one dimension of the display address and another portion of the second device is allocated to the least significant bits of another dimension of the display address, thereby forming a two-dimensional cell of storage locations on a single page corresponding to a region on the display. The page can be extended by using a plurality of random-access memory devices and selecting one of the devices using the least significant bits of one dimension of the display address. An addressing scheme is provided which permits simultaneous 'page mode' writing of data into multiple storage locations representing contiguous pixels of the display. A mechanism is also provided for reading back data from a plurality of storage locations representing contiguous pixels on the display and storing the data in a temporary storage-shift register for subsequent manipulation.

Raster graphics display refresh memory architecture offering rapid

An apparatus for generating a video signal suitable to cause a representation of repetitive waveform to be displayed on a raster scan display device comprises a differential amplifier which forms an output signal representing a clipped version of the instantaneous difference between the voltage of the waveform and a voltage representing the position of the raster scan line then being executed. An absolute value circuit receives the output signal of the differential amplifier and generates an output signal representing the absolute value of the output signal of the differential amplifier with respect to a reference level. The absolute value signal is inverted and level shifted, and is amplified so that its excursions are of predetermined magnitude.

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Beaverton, OR, United States of America

Robert A Bruce