Intel Corporation

Robert A Branch

Anand K Enamandram

Kerry Vander Kamp

Murugasamy K Nachimuthu

Mahesh S Natu

Sundar Muthusamy

Siddhartha Chhabra

Hormuzd M Khosravi

Wei P Chen

Yen-Cheng Liu

Andrew J Fish

Joshua Boelter

Todd A Schelling

Tiffany J Kasanicky

Manjula Peddireddy

Monam Agarwal

James Goffena

Jason Voelz

Wei Chen

Rita Deepak Gupta

An apparatus comprising a first memory interface of a first type to couple to at least one first memory device; a second memory interface of a second type to couple to at least one second memory device; and circuitry to interleave memory requests targeting contiguous memory addresses among the at least one first memory device and the at least one second memory device.

Interleaving of heterogeneous memory targets

Systems, methods, and apparatuses to implement spatially unique and location independent persistent memory encryption are described. In one embodiment, a system on a chip (SoC) includes at least one persistent range register to indicate a persistent range of memory, an address modifying circuit to check if an address for a memory store request is within the persistent range indicated by the at least one persistent range register, and append a unique identifier value, for a component corresponding to the memory store request for the address, to the address to generate a modified address and output the modified address as an output address when the address is within the persistent range, and output the address as the output address when the address is not within the persistent range, and an encryption engine circuit to generate a ciphertext based on the output address.

Circuitry and methods for spatially unique and location independent persistent memory encryption

Techniques and mechanisms for identifying a memory access resource which is to be a target of an access request. In an embodiment, a processor comprises route tables which are to provide entries corresponding to different respective memory access resources which are coupled to the processor. The processor further comprises a list of items which each correspond to a different respective range of addresses, wherein the items each include an identifier of a respective route table, and an identifier of a respective index offset. Based on an address of the access request, a decoder circuit of the processor searches the list to identify a corresponding one of the items. In another embodiment, the decoder circuit accesses a route table entry, based on the search, to determine how the access request is to be directed to a particular memory access resource.

Accessing a memory using index offset information

Systems, apparatuses and methods may provide for technology that detects a misalignment condition, wherein the misalignment condition includes a memory map being misaligned with a granularity of a register, automatically appends a protected range to the memory map, wherein the protected range eliminates the misalignment condition, and defines an operational characteristic of the memory map via the register. In one example, the protected range is a non-existent memory (NXM) range appended via a source address decoder (SAD) rule, the register is a memory type range register (MTRR), and the operational characteristic is a cache characteristic.

Technology to ensure sufficient memory type range registers to fully cache complex memory configurations

Technology for a system is described. The system can include one or more processors. The system can include a memory associated with the one or more processors. The system can include a memory controller comprising logic to create a reserved memory region in a system physical address (SPA) map. The memory controller can comprise logic to detect when the one or more processors are brought online. The memory controller can comprise logic to map the memory associated with the one or more processors that are brought online to the reserved memory region in the SPA map.

Devices and systems to reduce the number of memory type range registers (MTRRS) used to map processor-associated memory

Memory mapping

The present disclosure relates to attempting to maintain and/or repair the embedded software components of a computer and, more specifically, to attempting to maintain and/or repair the embedded software components of a server utilizing a service processor.

Embedded agent for self-healing software

A method of chaining interrupt service routines comprises creating a chain handler module and replacing an instruction in an existing interrupt service routine with a branch directed to the chain handler module.

Method and apparatus for chaining interrupt service routines

A method for tracking agents across loss of state events is described. After determining the number of terminal agents within a hierarchical agent system, an algorithm forms a first matrix containing data identifying agents within the hierarchical agent system. After a potential loss of state event has occurred, the algorithm forms a second matrix containing data identifying agents within the hierarchical agent system and compares the first matrix to the second matrix. If the matrices are identical, no agent switch occurred during the potential loss of state event. If the matrices are not identical, at least one agent switch occurred during the potential loss of state event.

Growing community of inventors

Hillsboro, OR, United States of America

Robert A Branch