Signetics

Ikanos Communications, Inc.

Philips Electronics North America Corporation

North American Philips Corp, Signetics Division

Robert A Blauschild

Behrooz Rezvani

Sanjay Bhandari

Dale Smith

Rouben Toumani

Edmond Toy

Daniel J Linebarger

A high efficiency line driver is disclosed. The line driver may be applied with equal advantage in wired and wireless communication media to amplify data signals with a minimum of power consumption. In an embodiment of the invention a line driver is disclosed which includes: at least one amplifier, a delay element, a control signal generator and a generator. The at least one amplifier includes at least one bias supply, a signal input and a signal output. The delay element accepts as an input the data signal and delays delivery of the data signal to the at least one line amplifier for amplification. The generator is responsive to a control signal to generate varying voltage levels corresponding thereto on the at least one bias supply of the at least one amplifier. The control signal generator is responsive to the input data signal to detect peaks therein and to generate the control signal corresponding thereto in advance of delivery of the data signal to the amplifier.

Method and apparatus for a high efficiency line driver

An apparatus and method for A/D conversion is provided. The apparatus provides for multi-channel A/D conversion. It may be used in any application in which A/D conversion of either a single signal or multiple signal sources is required. Such applications include X-DSL communications. The apparatus and method allows A/D converters to be fabricated with reduced cost and power when compared with prior art designs. The A/D converter comprises a sampler, a converter and a logic. The sampler includes an input coupled with at least one analog information signal. The sampler repetitively provides at least one pre-sample together with a sample of the analog information signal. The sampling interval between the samples is substantially greater than a pre-sample interval between the pre-sample and the corresponding sample. The converter includes a bit line output and at least one input coupled with the output of said sampler. The converter is responsive to the pre-sample at the input to output a first bit signal corresponding to at least one significant bit of the pre-sample at the bit line output. The converter is further responsive to the sample at the input, to output a second bit signal corresponding to at least one significant bit of the sample at the bit line output. The logic is coupled with the bit line output of said converter. The logic combines the first bit signal and the second bit signal into a composite digital sample of the pre-sample together with the sample.

A/D multi-channel architecture

Mobility in an FET is used as a time standard to develop a resistance (or a transconductance or a current) reference which may be fully integrated and which is temperature stable to an arbitrary desired accuracy (or which varies with temperature in a desired fashion). The large temperature dependence of mobility is compensated (or adjusted to a desired variation characteristic) by applying a gate bias voltage having a predetermined variation in value with respect to temperature. In one embodiment the bias voltage of the FET is given a temperature dependence which results in the drain current of the FET being substantially constant with respect to temperature. This current is then used to charge or discharge a capacitor, yielding a precise R-C product which may be implemented fully in integrated form.

Fully integrated reference circuit having controlled temperature

A new logic family is identified that achieves much better speeds than CML logic gates. This new logic family operates with multiple inputs and a single logic level, using differential pairs of transistors for each input transistor of the multiple input. This new logic family enables high speed operation, or higher speed, than the prior art, together with lower operating current and a power-delay enhancement significantly increased over the prior art.

Logic family for low voltage high-speed applications

A highly accurate current-limiting circuit prevents an output current (I.sub.OUT) flowing through an output line (L.sub.OUT) from exceeding a specified value (I.sub.LIM) of an input current (I.sub.IN) flowing through an input line (L.sub.IN). The circuit contains a first channel device (10) controlled by a first reference voltage (V.sub.REF1), a current source (12) that supplies a reference current (I.sub.REF), a second channel device (14) controlled by a second reference voltage (V.sub.REF2), a current bypass device (16), and a bypass control system (18). The current gain below the specified value of the input current is close to one. By suitably choosing certain of the circuit parameters, the circuit operates in a substantially temperature-independent manner.

Unity-gain current-limiting circuit

A circuit switches with a hysteresis defined by separately controllable thresholds which can be made largely independent of temperature and fabrication conditions. The circuit contains a pair of differential portions (21 and 22) and an arithmetic component (24). The hysteresis is introduced into the circuit by using positive feedback to control the position of a switch (23) in such a manner as to change the transconductance of the circuit as it is switching.

Switching circuit with hysteresis

An input portion (4, 6) of a differential amplifier circuit amplifies a differential input signal to produce an amplified signal between a pair of terminals. A summing section contains two complementary pairs of like-polarity amplifiers (13, 14 and 19, 20). Each has a first flow electrode, a second flow electrode, and a control electrode. A substantially constant bias voltage is supplied to the control electrodes of the first pair (13, 14) whose second electrodes are respectively coupled to the second electrodes of the second pair (19, 20). Their first electrodes are respectively coupled to the terminals and to corresponding impedance elements (11, 12). The control electrodes of the second pair are coupled together to receive a voltage dependent on the voltage at the second electrode of one (13) of the first pair so as to produce a representative output signal at the second electrode of the other (14) of the first pair.

Differential amplifier circuit

An absolute-value analog-to-digital converter containing a chain of matched main absolute-value differential amplifiers (A.sub.1 -A.sub.N) has a gain control for regulating the gain of each main amplifier utilizing an auxiliary absolute-value differential amplifier (A.sub.GC) matched to the main amplifiers. An offset control in the converter drives the offsets of the amplifiers toward zero by using a further absolute-value differential amplifier (A.sub.OC) matched to the other amplifiers. The gain and offset control are implemented with suitable feedback circuitry.

Analog-to-digital converter using absolute-value conversion

A bipolar impedance buffer contains an input transistor (Q1) whose emitter is coupled to that of a like-polarity intermediate transistor (QN). Its collector is coupled to the base of a like-polarity output transistor (QO), while its base is coupled to the collector of an opposite-polarity transistor (QP). A resistor (RN) coupled between the base and collector of the intermediate transistor significantly reduces the output settling time.

Impedance buffer with reduced settling time

A differential amplifier circuit contains a pair of complementary input portions (3, 5 and 4, 6). The input portions amplify a common differential input signal to produce corresponding amplified differential signals which are supplied to a summing section that operates as a modulated current mirror to produce an output signal representative of the input signal. The summing section contains a pair of like-polarity first and second amplifiers (13 and 14) and a pair of like-polarity third and fourth amplifiers (19 and 20) complementary to the other amplifiers. A pair of impedance elements (11 and 12) are coupled between a first voltage supply (ground reference) and the third and fourth amplifiers. A pair of current sources, typically impedance elements (8 and 9), are coupled between a second voltage supply (+B) and the first and second amplifiers. An important feature of this circuit is that the output signal changes with the differential portion of the input signal as its common-mode portion varies over the entire voltage range between the levels of the supplies.

Differential amplifier circuit with rail-to-rail capability

A linear transconductance amplifier includes a differential transconductance amplifier stage and a differential correction amplifier stage. In order to achieve linear operation over a wide dynamic range, the nonlinearities generated in the transconductance amplifier stage are substantially cancelled by the nonlinearities generated in the correction amplifier stage. This is accomplished by cross-coupling the two stages and establishing the relative gain of the correction amplifier stage with respect to the transconductance amplifier stage such that the desired cancellation occurs. In a preferred embodiment, optimum cancellation occurs when the gain of the correction amplifier stage is substantially one-half the gain of the transconductance amplifier stage.

Linear transconductance amplifier

A temperature stable voltage reference utilizes an enhancement field effect transistor and a depletion field effect transistor each connected in series with a current source. A differential amplifier has its input terminals separately connected between each of the field effect transistors and their respective current supplies. An input terminal of the field effect transistor is utilized as the reference voltage and is also connected to the gate of one of the field effect transistors, the gate of the other field effect transistor being connected to a reference potential.

Stable field effect transistor voltage reference

A logic circuit for converting a triple state input to a binary output having a single line ternary input and a two line binary output. A pair of output transistors provide the two line binary output, and means are provided for driving both of these output transistors, such that three different binary output states result from the ternary input states of low, high and open (or floating), respectively.

Triple state to binary converter

A low resistance closed feedback loop regulated current source for supplying a load, the source being of the type including a transistor having input and output electrodes respectively connected between voltage input and current output terminals, and said transistor having a control electrode. The feedback loop includes amplifying means having an output connected to the transistor control electrode and having first and second inputs providing differential current gain for signal current at said inputs and for maintaining minimum differential voltage between said inputs. First and second PN semiconductor structures having first and second electrodes and having dissimilar junction boundary areas are provided with the first electrodes of said structures being connected to the respective first and second inputs of the amplifying means. A resistor is provided connected between the second electrode of the structure having the greater boundary area and the second electrode of the remaining structure. Means is provided coupled to sense current output of said source and is connected to the second electrode of said remaining structure for providing a feedback signal which causes the output of said current source to assume a predetermined value.

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Los Altos, CA, United States of America

Robert A Blauschild