International Business Machines Corporation

Robert A Blackburn

Robert O Dryfoos

Mark Richard Gambino

Peter Grimm Sutton

Michael J Shershin

Keith N Langston

Glenn W Sears, Jr

Gary A Fisher, Sr

Barry M Baker

Leslie F Sutton

William R Cohen

Robert Ochs Dryfoos

Michael J Shersin

A method and system is disclosed for dispatching tasks to multiple processors that all share a shared memory. A composite queue size for multiple work queues each having an associated processor is determined. A queue availability flag is stored in shared memory for each processor work queue and is set based upon the composite queue size and the size of the work queue for that processor. Each queue availability flag indicates availability or unavailability of the work queue to accept new tasks. A task is placed in a selected work queue based on that work queue having an associated queue availability flag indicating availability to accept new tasks. The data associated with task dispatching is maintained so as to increase the likelihood that valid copies of the data remain present in each processor's local cache without requiring updating do to their being changed by other processors.

Task dispatching based on composite queue size and upper and lower compare values

A method and system is disclosed for selecting a work queue associated with a processor within a multiple processor architecture to assign a new task. A local and a remote queue availability flag is maintained to indicate a relative size of work queues, in relationship to a mean queue size, for each processor in a multiple processor architecture. In determining to which processor to assign a task, the processor evaluates its own queue size by examining its local queue availability flag and evaluates other processor's queue sizes by examining their remote queue availability flags. The local queue availability flags are maintained asynchronously from task assignment. Remote flags are maintained at time of task assignment. The presented algorithm provides improved local processor queue size determinations in systems where task distribution processes execute with lower priorities that other tasks.

Work queue selection on a local processor within a multiple processor architecture

A method for selecting a processor to be acquired in a virtual, shared computing environment includes initiating a first selection phase to attempt to acquire a last relinquished processor of the shared computing environment, and initiating a second selection phase in the event of a failure of the first selection phase in acquiring the last relinquished processor. The second selection phase further includes a round-robin selection process for presently relinquished processors.

Method for efficient utilization of processors in a virtual shared environment

An exemplary embodiment of the present invention is a method for dynamically managing a hash pool data structure. A request to insert a new key value into a hash pool data structure that includes at least one index level is received. An insertion location is calculated for the new key value in response to the new key value and to existing key values in the hash pool data structure. The insertion location includes an index level. A new index level is added at the insertion location if the index level is not the maximum number of index levels in the hash pool data structure; if the insertion location contains a chain of existing key values with a length equal to the maximum chain length; and if the new index record locations of the new key value and the existing key values are dispersed. The insertion location is updated in response to adding a new index record and the new key value is inserted into the insertion location. An additional embodiment includes a system and storage medium for dynamically managing a hash pool data structure.

Method and system for dynamically managing hash pool data structures

A method and system for cache memory congruence class management in a data processing system. A selected address within a data processing system will typically have a single real address, but may have multiple virtual addresses within multiple virtual address spaces in a multi-tasking system, each virtual address space including a segment index, a page index and a byte index. A memory cache may be utilized to improve processor performance by hashing a portion of each virtual memory address to an address within a congruence class in the cache; however, when the cache contains a greater number of congruence classes than the number of different byte index addresses the virtual memory addresses of a single real memory address may hash to different congruence classes, reducing the ability of the processor to rapidly locate data within the cache. The method and system prevents this problem by first determining whether or not a virtual memory address exists within any virtual memory space in the system which corresponds to a selected address in real memory, in response to a request for a virtual memory address corresponding to that selected address. If such a virtual memory address already exists, a new virtual memory address is assigned such that the new virtual memory address will hash to the same congruence class as the existing virtual memory address, greatly enhancing the processor's efficiency at retrieving data within the cache. In the event no existing virtual memory address within the data processing system corresponds to the selected address a virtual memory address may be arbitrarily assigned.

Method and system for cache memory congruence class management in a data

A method and system are disclosed for efficiently managing task memory in a multi-tasking data processing system having a processor for processing multiple tasks, task memory associated with each task, main system memory and multiple data records stored within direct access storage. A data record is copied from direct access storage into a buffer in main system memory in response to an access of that data record by a particular task. A buffer within that task's virtual memory is then mapped to the data record and a write protect bit is associated with the task memory buffer. Thereafter, any attempt to store data into the buffer will temporarily halt processing of the task until a copy of the data record is written to a second buffer. Task processing is then resumed, after modifying the task's page table to reference the second buffer, and the task is then permitted to store data within the second buffer. In this manner, a second buffer copy of the data record is only created in response to an attempted modification of the data record, thereby minimizing the processor and memory assets required to manage data records in a multi-tasking data processing system.

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Hopewell Junction, NY, United States of America

Robert A Blackburn