Cadence Design Systems, Inc.

Other

Carnegie Mellon University

Neolinear, Inc.

Rob A Rutenbar

Elias Lee Fallon

Amith Singhee

Rodney Phelps

Edward Lin

Hongzhou Liu

L Richard Carley

Kai Hung Yu

Regis R Colwell

Prakash Gopalakrishnan

Ronald Alan Rohrer

Sonia Singhal

Patrick J Bourke

James D Ma

Claire F Fang

Anthony J Gadient

Donald B Reaves

A hardware acoustic scoring unit for a speech recognition system and a method of operation thereof are provided. Rather than scoring all senones in an acoustic model used for the speech recognition system, acoustic scoring logic first scores a set of ciphones based on acoustic features for one frame of sampled speech. The acoustic scoring logic then scores senones associated with the N highest scored ciphones. In one embodiment, the number (N) is three. While the acoustic scoring logic scores the senones associated with the N highest scored ciphones, high score ciphone identification logic operates in parallel with the acoustic scoring unit to identify one or more additional ciphones that have scores greater than a threshold. Once the acoustic scoring unit finishes scoring the senones for the N highest scored ciphones, the acoustic scoring unit then scores senones associated with the one or more additional ciphones.

Acoustic scoring unit implemented on a single FPGA or ASIC

The present invention relates to a low-power speech recognition system. In one embodiment, the speech recognition system is implemented in hardware and includes a backend search engine that operates to recognize words based on senone scores provided by an acoustic scoring stage. The backend search engine includes a scoring engine, a transition engine, and a language model engine. For a frame of sampled speech, the scoring engine reads active acoustic unit models from external memory, updates the active acoustic unit models based on corresponding senone scores received from an acoustic scoring stage, and writes the active acoustic unit models back to the external memory. The scoring engine enters a low-power state until processing for a next frame of sampled speech is to begin. The transition stage identifies any completed words, and the language model engine processes completed words to identify words that are likely to follow in a subsequent frame.

Hardware-implemented scalable modular engine for low-power speech recognition

A hardware implemented backend search stage, or engine, for a speech recognition system is provided. In one embodiment, the backend search engine includes a number of pipelined stages including a fetch stage, an updating stage which may be a Viterbi stage, a transition and prune stage, and a language model stage. Each active triphone of each active word is represented by a corresponding triphone model. By being pipelined, the stages of the backend search engine are enabled to simultaneously process different triphone models, thereby providing high-rate backend searching for the speech recognition system. In one embodiment, caches may be used to cache frequently and/or recently accessed triphone information utilized by the fetch stage, frequently and/or recently accessed triphone-to-senone mappings utilized by the updating stage, or both.

Hardware implemented backend search engine for a high-rate speech recognition system

A method and system for rapidly modeling and simulating intra-die variations in an integrated circuit are disclosed. In one embodiment, each logic gate in an integrated circuit has a characteristic to be simulated, where the characteristic of the gate is a function of one or more parameters having intra-die variations. For each parameter, a model of intra-die variation of the parameter is generated such that a number of random variables in the model is compressed to a reduced number (r) of random variables based on a spatial correlation of the intra-die variation of the parameter. Then, using a Quasi Monte Carlo (QMC) technique, the integrated circuit is simulated based on the model of the intra-die variation of each of the one or more parameters.

Method and apparatus for rapidly modeling and simulating intra-die statistical variations in integrated circuits using compressed parameter models

The invention provides methods for enhancing circuit reliability under statistical process variation. For highly replicated circuits such as SRAMs and flip flops, a rare statistical event for one circuit may induce a not-so-rare system failure. To combat this, the invention discloses the method called 'Statistical Blockade,' a Monte Carlo-type technique that allows the efficient filtering&#x2014;blocking&#x2014;of unwanted samples insufficiently rare in the tail distributions of interest, with speedups of 10-100&#xd7;. Additionally, the core Statistical Blockade technique is further extended in a 'recursive' or &#x201c;bootstrap&#x201d; formulation to create even greater efficiencies under a much wider variety of circuit performance metrics, in particular two-sided metrics such a Data Retention Voltage (DRV) which prior Monte Carlo techniques could not handle.

Method and apparatus for sampling and predicting rare events in complex electronic devices, circuits and systems

A method and system for modeling uncertainties in integrated circuits, systems and fabrication processes may include defining interval values for each uncertain component or parameter in a circuit or system. The method may also include replacing scalar operations with interval operations in an algorithm and discontinuing interval operations in the algorithm in response to a predetermined condition. The method may also include generating a plurality of scalar samples from a plurality of intervals and determine a distribution of each uncertain component or parameter from the scalar samples of the intervals.

Method and system for modeling uncertainties in integrated circuits, systems, and fabrication processes

A method for determining component placement in a circuit includes forming a tree structure that defines the placement of each of a plurality of components associated with the tree structure on a first side, a second side or on both sides of a symmetry line, with at least one component tagged for symmetric placement on both sides of a symmetry line; performing at least one search of the tree structure to determine an initial placement of a subset of the components; and performing another search of the tree structure to determine a final placement of the subset of components whereupon at least a part of each component tagged for symmetric placement is positioned on each side of the symmetry line. The method can be embodied as instructions stored on a computer readable medium which, when executed by a processor, cause the processor to implement the method.

Method for generating constrained component placement for integrated circuits and packages

In a method of automatically sizing and biasing a circuit, a database is provided including a plurality of records related to cells that can be utilized to form an integrated circuit. A cell parameter of a cell for a circuit is selected and compared to cell parameters residing in the records stored in the database. One record in the database is selected based upon this comparison and a performance characteristic of the circuit is determined from this record.

Method for automatically sizing and biasing circuits by means of a database

To identify high quality design points in a circuit design, a plurality of design points is generated for the circuit. A subset of the design points is allocated to a design population. A cost is then determined for each allocated design point. From a subset of the allocated design points, a plurality of new design points is generated for the circuit. The cost for each new design point is then determined and each new design point having a cost that is the same or more favorable than the most favorable cost associated with the allocated design points is allocated to the design population. The design points allocated to the design population can then be displayed for selection of one of said allocated design points having desired performances of the circuit.

Method and apparatus for quantifying tradeoffs for multiple competing goals in circuit design

A method of determining the position of devices in a circuit layout includes defining an array of cells and defining a plurality of device outlines in the array, with each device outline received in at least one cell. A set of size constraints is established that expresses the size of each device. For each column and each row of cells having a plurality of device outlines contained completely therein, the position of one of the device outlines is determined and a constraint is established for each other device outline that expresses its position with respect to the position of the one device outline. A spacing constraint for each pair of adjacent device outlines is established that expresses a spacing therebetween. The foregoing constraints are solved simultaneously and a layout of the device outlines is generated in accordance with the solution.

Method and apparatus for exact relative positioning of devices in a semiconductor circuit layout

A plurality of member devices is defined in a conformal outline having a pair of spaced parallel sides. Associated with each member device is a spacing constraint that sets a minimum distance the member device can be spaced from another member device and each side of the conformal outline. The spacing between member devices and/or the sides of the conformal outline are increased and/or decreased as necessary to minimize the area of the conformal outline that the member devices are received in with no violation of the spacing constraints while excluding from the conformal outline all or part of any nonmember devices defined therein.

Integrated circuit design layout compaction method

A conformal outline of a well which is to receive elements of a circuit is formed from one or more candidate rectangles which enclose input rectangles. The one or more candidate rectangles are determined based upon a cost of the candidate rectangles determined therefor based on the overlap of the candidate rectangles with one or more penalty or avoid rectangles. Each input rectangle represents an area where it is desired to place elements of the circuit and each penalty or avoid rectangle represent an area where it is desired to avoid placing elements of the circuit. To determine the candidate rectangle(s) having the most advantageous cost, a side and/or an edge of each candidate rectangle is positioned at or near plural locations where the sides and/or edges of the input rectangles reside and a cost is determined therefor. The candidate rectangle(s) having the most favorable cost are then utilized as solution rectangles for the conformal outline.

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Pittsburgh, PA, United States of America

Rob A Rutenbar