Marvellworld Trade Ltd.

Marvell International Limited

Roawen Chen

Albert M Wu

Chuan-Cheng Cheng

Shuhua Yu

Shiann-Ming Liou

Runzi Chang

Chien-Chuan Wei

Scott Wu

Sehat Sutardja

Po-Chien Chang

Chung Chyung Han

Chung Chyung (Justin) Han

Embodiments of the present disclosure provide an apparatus comprising a semiconductor substrate having a first surface, a second surface that is disposed opposite to the first surface, wherein at least a portion of the first surface is recessed to form a recessed region of the semiconductor substrate, and one or more vias formed in the recessed region of the semiconductor substrate to provide an electrical or thermal pathway between the first surface and the second surface of the semiconductor substrate, and a die coupled to the semiconductor substrate, the die being electrically coupled to the one or more vias formed in the recessed region of the semiconductor substrate. Other embodiments may be described and/or claimed.

Package assembly including a semiconductor substrate in which a first portion of a surface of the semiconductor substrate is recessed relative to a second portion of the surface of the semiconductor substrate to form a recessed region in the semiconductor substrate

Embodiments of the present disclosure provide a method, comprising providing a semiconductor substrate having (i) a first surface and (ii) a second surface that is disposed opposite to the first surface, forming one or more vias in the first surface of the semiconductor substrate, the one or more vias initially passing through only a portion of the semiconductor substrate without reaching the second surface, forming a dielectric film on the first surface of the semiconductor substrate, forming a redistribution layer on the dielectric film, the redistribution layer being electrically coupled to the one or more vias, coupling one or more dies to the redistribution layer, forming a molding compound to encapsulate at least a portion of the one or more dies, and recessing the second surface of the semiconductor substrate to expose the one or more vias. Other embodiments may be described and/or claimed.

Recessed semiconductor substrates and associated techniques

A system including an interface module to interface a solid-state disk controller to a computing device. A memory control module exchanges data with the computing device via the interface module and caches the data in a solid-state memory controlled by the solid-state disk controller. A network interface module communicates with the computing device via the interface module and interfaces the computing device to a wireless network. A crossbar module has a master bus (Mbus) interface bridged to an advanced high-performance bus (AHB). A memory communicates with one or more of the network interface module and the crossbar module via one or more of the Mbus interface and the AHB. In response to data being cached from the computing device to the solid-state memory or data cached in the solid-state memory being output to the computing device, the network interface module buffers data received from the wireless network in the memory.

Solid-state disk with wireless functionality

A solid-state disk (SSD) controller includes a first integrated circuit (IC) that includes an interface module, a memory control module, and a wireless network interface module. The interface module externally interfaces the SSD controller to a computing device. The memory control module controls solid-state memory, receives data from the computing device via the interface module, and caches the data in the solid-state memory. The wireless network interface module communicates with the computing device via the interface module and allows the computing device to connect to a wireless network.

An integrated circuit includes a bulk technology integrated circuit (bulk IC) including a bulk silicon layer and complementary MOSFET (CMOS) transistors fabricated thereon. The integrated circuit also includes a single transistor dynamic random access memory (1T DRAM) cell arranged adjacent to and integrated with the bulk IC.

Method for fabricating 1T-DRAM on bulk silicon

A fuse structure, an integrated circuit including the structure, and methods for making the structure and (re)configuring a circuit using the fuse. The fuse structure generally includes (a) a conductive structure with at least two circuit elements electrically coupled thereto, (b) a dielectric layer over the conductive structure, and (c) a first lens over both the first dielectric layer and the conductive structure configured to at least partially focus light onto the conductive structure. The method of making the structure generally includes the steps of (1) forming a conductive structure electrically coupled to first and second circuit elements, (2) forming a dielectric layer thereover, and (3) forming a lens on or over the dielectric layer and over the conductive structure, the lens being configured to at least partially focus light onto the conductive structure. The method of (re)configuring a circuit generally includes the steps of (i) irradiating at least one lens on or near a surface of the circuit sufficient to electrically disconnect a corresponding first fuse positioned under the lens and disable a first configuration of the circuit, and (ii) irradiating at least one other lens on or near the surface of the circuit sufficient to electrically disconnect a corresponding second fuse positioned under that lens and enable a second configuration of the circuit. The structure and methods advantageously provide fuse structures having improved reliability and smaller chip area, thereby increasing the yield of the manufacturing process and the numbers of die per wafer (both gross and good).

Methods of making and using fuse structures, and integrated circuits including the same

Fuse structures, methods of making and using the same, and integrated circuits including the same

A structure configured to disconnect circuit elements. The structure generally includes a dielectric layer over a light-absorbing structure, and a lens over the dielectric layer and the light-absorbing structure, configured to at least partially focus light onto the light-absorbing structure. The light-absorbing structure absorbs a first wavelength of light with a minimum threshold efficiency, the lens is substantially opaque to the first wavelength of light, and the dielectric layer is substantially transparent to the first wavelength of light. The structure advantageously provides improved reliability and smaller chip area, thereby increasing the yield of the manufacturing process and the numbers of die per wafer (both gross and good).

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San Jose, CA, United States of America

Roawen Chen