Nagravision S.a.

Roan Hautier

Jerome Perrine

Marco Macchetti

Karine Villegas

Fabien Gremaud

Claudio Favi

Jérôme Perrine

Jean-Marie Martin

Sebastien Bellon

A method is provided in which digital information is stored in a plurality of segments in an external memory. The method is performed by a processing device and comprises the steps of loading a first integrity table containing a plurality of first integrity elements respectively authenticating the plurality of segments of digital information, and an associated digital signature of the plurality of first integrity elements, from the external memory; verifying the digital signature associated with the first integrity table, and loading segments of digital information in a protected form from the external memory to the processing device.

Method for processing digital information

A secure element has a secure processor for securely processing the digital information stored in a memory external to the secure element, and a loading and pre-processing system configured to load the digital information from the external memory into the secure element, and pre-process said digital information by executing a cryptographic algorithm before processing said digital information by the secure processor. The system reads a version number of the digital information that has been loaded, from an internal memory of the secure element, and uses said version number in executing the cryptographic algorithm.

Secure element for securely processing digital information

A method if provided for securely processing digital information performed by a secure element having a secure processor. The method includes loading the digital information from an external memory into the secure element; segmenting the digital information into words of digital information (Wij,k), generating error-detection codes or error-correction codes from said words of digital information and associating said error-detection codes with the corresponding words; transferring the words of digital information and the associated error-detection codes or error-correction codes to the secure processor; and in the secure processor, verifying the words of digital information based on the associated error-detection codes or error-correction codes before processing the digital information contained in said words.

Method for securely processing digital information in a secure element

A method for detecting perturbations in a logic circuit including a plurality of datapaths coordinated by a clock signal and at least one test circuit having a programmable length datapath for varying a test propagation delay. The test circuit further including inputs, an output and an error generator for providing an error in case that the output is different than an expected output for the inputs. The test circuit having a calibration mode including determining a critical propagation delay by varying the programmable length datapath until the error generator outputs an error, adjusting the programmable length datapath to include therein a tolerance delay, and switching into a detection mode configured to detect a perturbation in the logic circuit along the programmable length datapath in case the error generator outputs an error.

Method for detecting perturbations in a logic circuit and logic circuit for implementing this method

An integrated circuit and a method of configuring a plurality of integrated circuits are disclosed. Each integrated circuit comprises a cryptographic key specific to it. Each integrated circuit comprises a cryptographic key specific to it. Each cryptographic key can be generated on the respective integrated circuit using a physical unclonable function and data associated with the cryptographic key, e.g. a configuration message comprising instructions for generating the cryptographic key using the physical unclonable function. The cryptographic key specific to the integrated circuit is not stored on the integrated circuit. Each of the plurality of integrated circuits are configured using a data file that is encrypted with the respective cryptographic key specific to the integrated circuit, circuit.

Integrated circuit personalisation

Method and system for personalizing a chip, intended to be integrated into a smart card, comprising a tester associated to an FPGA device connected to the chip, the chip being part of a wafer comprising a plurality of chips and a disposable hardware module for verifying presence of the chip on the wafer. The tester sends a first secret code to the FPGA device, which commands the chip to initiate a test mode activation. The FPGA device encrypts a second secret code by using a secret encryption algorithm parameterized with a random number received from the chip and the first secret code to obtain a first cryptogram which is sent to the chip. The chip determines a second cryptogram by carrying out a Boolean function over a result obtained by decryption of the first cryptogram using the inverse algorithm parameterized with the random number and the first secret code. The second cryptogram is compared with a result obtained by carrying out the Boolean function over the second secret code temporarily stored on the chip. The FPGA device personalizes the chip only if the second cryptogram matches the calculated result.

Method and system for smart card chip personalization

The present invention provides a method and an apparatus for encrypting and decrypting digital information while imparting a high level of security on the encrypted digital information. A mixed-mode digital-analogue encryption and decryption technique is proposed, which minimizes the probability of an unintended recipient of the thus encrypted information being able to decrypt the information using known reverse engineering techniques.

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Cuarnens, Switzerland

Roan Hautier