Advanced Micro Devices Corporation

Rizwan M Farooq

Harand Gaspar

Chong Chang Lin

Melissa D Cooper

Ehab F Barsoum

An integrated network test device has network logic configured for performing prescribed network device operations and outputting network data based on a media independent interface (MII) based protocol, first test logic configured for performing prescribed test operations on the network data and outputting test data based on the MII-based protocol, and second test logic configured for converting the test data, output from the first test logic according to the MII-based protocol, into analog-based signals for transmission on twisted pair media. The integration of the network logic, the first test logic, and the second test logic dramatically simplifies testing systems, since the integrated network test device can be coupled to test equipment such as a traffic generator, using a relatively simple twisted pair or 10 BaseT connection, as opposed to more complex MII cabling.

Arrangement for converting between a media independent interface and a twisted pair medium using a field programmable gate array

An arrangement for testing flow control logic in a network device such as a network switch includes a traffic generator configured for transmitting pause frames having prescribed pause values. The network device is configured for continuously transmitting data frames on a network medium. The traffic generator is configured for outputting a first pause frame to the network device that specifies a first pause interval on the order of ten minutes, followed by outputting during the first pause interval a second pause frame specifying a second pause interval substantially less than the first pause interval, for example on the order of ten seconds. The traffic generator is configured for measuring a time interval between transmission of the first pause frame and reception of subsequent data frames from the network device for evaluation of the flow control logic. Hence, the traffic generator can determine whether the second pause frame causes the flow control logic to cancel the first pause frame.

Arrangement for testing pause frame response in a network switch

A test system for a design of a network device under test includes an oscillator configured for generating a first clock signal for a first clock domain, and field programmable gate arrays. Each field programmable gate array is configured for performing device operations according to the first clock domain and transferring data to another device at a network data rate based on a second clock domain. Each field programmable gate array includes clock conversion logic configured for generating a second clock signal for the second clock domain, based on the first clock signal. Hence, the generation of the second clock signal within each field programmable gate array ensures that timing accuracy is maintained, enabling communication between the field programmable gate arrays at high-speed data rates based on the second clock domain.

Arrangement for generating multiple clocks in field programmable gate arrays of a network test system

A method of testing a port register of an integrated network device includes establishing a programmable value for a register of an integrated network device. The register is programmed with a prescribed value configured to represent the programmable value. A read value is read from the register following the programming with the prescribed value. The programming step is validated by comparing the read value with the programmable value.

Arrangement for testing programmed port registers of integrated network device by reading-back values from the port registers

A test system for a design of a network device under test, having multiple design modules, includes multiple field programmable gate arrays configured for performing operations of the respective design modules. The test system also includes shared resources, where each field programmable gate array includes resource control logic for accessing the shared resources according to a prescribed shared resource protocol. Hence, the resource control logic of each of the field programmable gate arrays cooperate to ensure there is no interference between the multiple field programmable gate arrays for the shared resources. Hence, a design can be partitioned into multiple field programmable gate arrays, enabling testing of large scale designs; moreover, the partitioning of the design into multiple FPGAs enables each design module to be separately controlled, enabling design revisions to different design modules as necessary, without any other modification to the remaining test system.

Arrangement for partitioning logic into multiple field programmable gate arrays

A device is provided for receiving RJ-45 plugs in corresponding jacks. Each RJ-45 plug has a lever arm movable from a locked position, locking the plug to a corresponding jack, to a released position permitting the plug to be removed from the corresponding jack. The device includes a body having a plurality of jacks therein. Each jack is constructed and arranged to receive at least a portion of a RJ-45 plug therein. A plug releasing mechanism is mounted with respect to the body and is constructed and arranged such that when at least two plugs are disposed in the locked position in corresponding jacks, movement of the plug releasing mechanism to an actuating position engages the lever arm of each of the plugs, moving the lever arms to the released position generally simultaneously.

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Santa Clara, CA, United States of America

Rizwan M Farooq