International Business Machines Corporation

Riyon W Harding

Kenneth Joseph Goodnow

Sebastian Theodore Ventrone

Jason Michael Norman

Charles Joseph Masenas

Francis A Kampf

Karl V Swanke

Gary R Doyle

Disclosed is an integrated circuit comprising a plurality of cores attached to at least one transmitter and receiver, an optical transmission network embedded within the wire levels of the integrated circuit, and wherein the transmitter and receivers send and receive data on the network. Also disclosed is a method of transmitting signals within an integrated circuit comprising an integrated circuit comprising a plurality of cores and optical paths, selecting an optical path from the plurality of optical paths for transmitting data, and transmitting the data on the selected optical path. Also disclosed is an integrated circuit comprising an optical transmission network, a plurality of cores, and a plurality of controllers, all three being operatively attached to each other.

Fiber optic transmission lines on an SOC

Operating code fixes are supplied to multiple processors utilizing the same operating code by storing the correction code fixes in a central RAM, and distributing the code fixes over a dedicated code fix bus to a local cache for each processor. The first processor encountering a code fix requests the code fix from the RAM, which then distributes the code fix over the code fix bus to all of the local caches which are automatically updated with the new code. The system is particularly applicable to an integrated circuit having multiple processors fabricated on a chip, wherein the RAM is on-chip and is connected to an off-chip EEPROM that loads corrected code fixes to the on-chip RAM at power-up.

Multiprocessor code fix using a local cache

A communication system for transmitting data between cores embedded in an integrated circuit on a silicon chip. Communication system includes transmitter circuitry for wirelessly transmitting data between cores and receiver circuitry for wirelessly receiving the transmission of data from other cores. Both transmitter circuitry and receiver circuitry may include of a phase-locked loop circuit having a voltage-controlled oscillator. Each core may transmit and receive data on a unique frequency with respect to other cores embedded in an integrated circuit on a silicon chip or transmit and receive data on the same frequency as other cores embedded in an integrated circuit on a silicon chip. Groups of cores may share transmitter and receiver circuitry.

Wireless communication system within a system on a chip

A random number generator () comprising a plurality of voltage islands () on a chip (), one or more latches () located on each of plurality of voltage islands (), with one or more latches () adapted to capture the voltage value of the respective voltage island on which they are located as an input value of one or more latches (), a control circuit () for randomly controlling the state of each of plurality of voltage islands () and for capturing an output value for each of one or more latches (), and a conversion circuit () for producing decimal numbers from the output value for each of one or more latches (). In one embodiment, control circuit () includes two or more clocks (), a multiplexer () for each of plurality of voltage islands (), and an enable circuit () for each of plurality of voltage islands ().

Random number generator

A communication system () for transmitting data between cores () embedded in an integrated circuit on a silicon chip (). Communication system () includes transmitter circuitry () for wirelessly transmitting data between cores () and receiver circuitry () for wirelessly receiving the transmission of data from other cores. Both transmitter circuitry () and receiver circuitry () may include of a phase-locked loop circuit () having a voltage-controlled oscillator (). Each core () may transmit and receive data on a unique frequency with respect to other cores embedded in an integrated circuit on a silicon chip () or transmit and receive data on the same frequency as other cores embedded in an integrated circuit on a silicon chip (). Groups of cores () may share transmitter and receiver circuitry (and).

An impedance controller comprises impedance control logic outputting an adjustable impedance and a comparator comparing the adjustable impedance with a reference voltage. The impedance control logic recalibrates said adjustable impedance only when said comparator indicates a change in impedance.

Growing community of inventors

Richmond, VT, United States of America

Riyon W Harding