Alliance Semiconductor Corporation

Zettacore, Inc.

Other

Cypress Semiconductor Corporation

North Carolina State University

Sandisk 3d LLC

Ritu Shrivastava

Chitranjan N Reddy

Perumal Ratnam

Kenneth J Mobley

Antonio R Gallo

Tom DeBolske

Franz Kreupl

Werner G Kuhr

Veena Misra

Thurman John Rodgers

Bruce L Prickett, Jr

William Koutny

Guru Mathur

Arya Bhattacherjee

Zhong Chen

C N Reddy

A memory device in a 3-D read and write memory includes memory cells. Each memory cell includes a resistance-switching memory element (RSME). The RSME has first and second resistance-switching layers on either side of a conductive intermediate layer, and first and second electrodes at either end of the RSME. The layers can be provided in a lateral arrangement, such as an end-to-end, face-to-face, L-shaped or U-shaped arrangement. In a set or reset operation of the memory cell, an electric field is applied across the first and second electrodes. An ionic current flows in the resistance-switching layers, contributing to a switching mechanism. An electron flow, which does not contribute to the switching mechanism, is reduced due to scattering by the conductive intermediate layer, to avoid damage to the steering element.

Memory cell with resistance-switching layers and lateral arrangement

Molecular memories, i.e., memories that incorporate molecules for charge storage, are disclosed. Molecular memory cells, molecular memory arrays, and electronic devices including molecular memory are also disclosed, as are processing systems and methods for manufacturing molecular memories. Methods of manufacturing molecular memories that enable semiconductor devices and interconnections to be manufactured monolithically with molecular memory are also disclosed.

Processing systems and methods for molecular memory

According to some embodiments, an article of manufacture comprises a substrate; a molecular layer on the substrate comprising at least one charge storage molecule coupled to the substrate by a molecular linker; a solid barrier dielectric layer directly on the molecular layer; and a conductive layer directly on the solid barrier dielectric layer. In some embodiments, the solid barrier dielectric layer is configured to provide a voltage drop across the molecular layer that is greater than a voltage drop across the solid barrier dielectric layer when a voltage is applied to the conductive layer. In some embodiments, the molecular layer has a thickness greater than that of the solid barrier dielectric layer. The article of manufacture contains no electrolyte between the molecular layer and the conductive layer.

Molecular memory devices including solid-state dielectric layers and related methods

A system for and a method of integrating SRAM cells and flash EPROM cells onto a single silicon substrate includes an area on the silicon substrate where a local oxidation of silicon (LOCOS) isolation technique is implemented and another area on the same silicon substrate where a shallow trench isolation (STI) technique is implemented. Further, this system and method also include flash EPROM cells implemented within the area of the substrate utilizing the LOCOS isolation technique and SRAM cells implemented within the area of the substrate utilizing the STI technique. Preferably, the LOCOS isolation technique is first implemented to define a flash area of the silicon substrate on which the flash EPROM cell is implemented. Before the LOCOS isolation technique is implemented, an SRAM area is masked. After the LOCOS isolation technique has been fully implemented, the flash area is then preferably masked and the STI technique is implemented in order to define the SRAM area of the silicon substrate on which the SRAM cell is implemented. After the STI technique is implemented, the flash EPROM and the SRAM cells are preferably formed. Thus, the SRAM cells and the flash EPROM cells are both implemented on the common silicon substrate, but yet are appropriately isolated from each other, as well as from other additional devices which may be further implemented on the same silicon substrate, while providing the advantages of respective isolation schemes for the two cells.

Method of and apparatus for integrating flash EPROM and SRAM cells on a common substrate

Method and apparatus for integrating flash EPROM and SRAM cells on a common substrate

The dynamic random access memory (DRAM) cells in a semiconductor chip are isolated from the peripheral circuitry by forming the DRAM cells directly in the substrate while the peripheral and other functional circuits are formed in wells that are isolated from the substrate. In addition to providing isolation, the placement of the DRAM cells also reduces the leakage current in the cells, thereby increasing the time that a DRAM cell can hold a charge without being refreshed.

Semiconductor chip that isolates DRAM cells from the peripheral circuitry and reduces the cell leakage current

A DRAM cell ( ) having a capacitor-over-bit line (COB) structure self-aligned to the word lines and bit lines is disclosed. Word lines ( ) and bit lines ( ) are formed with insulating structures that include insulating sidewalls. The word line insulating structure includes an etch barrier layer ( ) that extends over a source region ( ). A first interlayer dielectric (ILD) ( ) insulates the word lines ( ) from the bit lines ( ) and a second ILD ( ) insulates the bit lines from a cell capacitor. A capacitor contact hole ( ), self-aligned with the bit lines and the word lines, is formed by etching through the first and second ILDs ( and ) to expose the etch barrier layer ( ) over the source region ( ). Portions of the bit line and word line exposed by the etch are protected by their respective insulating structures. The exposed etch barrier layer ( ) over the source region ( ) is cleared and a storage capacitor is formed having a contact that extends into the contact hole to make contact with the source region ( ).

DRAM cell having storage capacitor contact self-aligned to bit lines and word lines

A flash EPROM cell ( ) is disclosed having increased capacitive coupling between a floating gate ( ) and a control gate ( ). Vertical structural elements ( and ) are formed on field oxide regions ( ) on opposing sides of the flash EPROM cell channel , in the channel width direction. The structural elements ( and ) include relatively vertical faces. The floating gate ( ) conformally cover the channel and the vertical faces of the structural elements ( and ). The control gate ( ) conformally covers the floating gate ( ). The vertical displacement introduced by the structural elements ( and ) increases the overlap area between the floating gate ( ) and the control gate ( ) without increasing the overlap area of the floating gate ( ) and the channel , resulting in increased capacitive coupling between the control gate ( ) and the floating gate ( ). A process is disclosed which enables the formation of the above structural elements ( and ) with dimensions that are smaller than those normally achievable by the minimum resolution of lithography equipment.

Flash EPROM memory cell having increased capacitive coupling and method of manufacture thereof

A flash EPROM array ( ) and method of manufacture is disclosed. Source regions ( ) are shared between the memory cells ( ) of row ( ) pairs, and are isolated from one another in the row direction by isolation regions . Low resistance source conductor members ( ) extend in the row direction and are formed over the source regions ( ) and make contact therewith in a self-aligned fashion. The architecture allows for source decoding and thus enables user programmable sector erase architecture.

Flash EPROM array with self-aligned source contacts and programmable sector erase architecture

Provided is a method of forming self-aligned contacts in salicided MOS devices that provides improved reliability and decreased resistance relative to conventional tungsten polycide processing. Self-aligned contacts in salicided MOS devices are also provided. The method makes use of a metal, preferably titanium or cobalt, which is deposited on the devices' gates and diffusion regions and converted to a silicide with a resistance substantially less than that of tungsten silicide, preferably by RTA processing. A self-aligned contact etch stop mask is then formed over the gates and a portion of sidewall spacers on the gates. The presence of this &ldquo;oversize&rdquo; self-aligned contact etch stop mask prevents shorting of the subsequently deposited contact interconnect material to the gates, while allowing silicidation of the diffusion regions as well as the gates with a low resistance silicide, thereby improving device reliability and decreasing resistance.

Self-aligned contacts for salicided MOS devices

A flash EPROM cell (10) is disclosed having increased capacitive coupling between a floating gate (28) and a control gate (32). Vertical structural elements (34a and 34b) are formed on field oxide regions (20) on opposing sides of the flash EPROM cell channel 20, in the channel width direction. The structural elements (34a and 34b) include relatively vertical faces. The floating gate (28) conformally cover the channel 20 and the vertical faces of the structural elements (34a and 34b). The control gate (32) conformally covers the floating gate (28). The vertical displacement introduced by the structural elements (34a and 34b) increases the overlap area between the floating gate (28) and the control gate (32) without increasing the overlap area of the floating gate (28) and the channel 20, resulting in increased capacitive coupling between the control gate (32) and the floating gate (28). A process is disclosed which enables the formation of the above structural elements (34a and 34b) with dimensions that are smaller than those normally achievable by the minimum resolution of lithography equipment.

Flash EPROM memory cell having increased capacitive coupling

A method of fabricating structures to reduce dielectric damage due to charging is easily incorporated into existing stacked gate fabrication processes. The conductive layers are patterned to form structures which are coupled to the substrate by a current passing device. Each current passing device is isolated from the control gate structures toward the end of the etch process, thereby providing a discharge path for the control gate structures throughout substantially all of the stacked gate etch step. First and second conductive layers are patterned with one or more masks to create stacked gate structures. The multiple masks minimize the exposed area of the second conductive layer during the etch process and so reduce the amount of charging on the gate structures. Each current passing device is preferably an interconnect via coupling the second conductive layer to the first conductive layer. The discharge path allows charge to travel from the second conductive layer through the via to the first conductive layer. From the first conductive layer the charge can travel to the substrate through a buried contact structure.

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Fremont, CA, United States of America

Ritu Shrivastava