Intel Corporation

Ritu Gupta

Stephen R Van Doren

Aravindh V Anantaraman

Ashok Jagannathan

Andrew J Herdrich

Anand K Enamandram

Philip Abraham

Embodiments of apparatuses, methods, and systems for flexible provisioning of coherent memory address decoders in hardware are disclosed. In an embodiment, an apparatus includes a plurality of address decoders and a plurality of configuration storage locations. Each of the configuration storage locations corresponds to one of the plurality of address decoders to configure the corresponding one of the plurality of address decoders to decode based on a corresponding one of a plurality of decode rules. Each of the plurality of configuration storage locations is allocated to one of a plurality of memory tiers.

Flexible provisioning of coherent memory address decoders in hardware

Techniques and mechanisms to facilitate access to a cache based on a dual basis partition scheme. In an embodiment, a first one or more registers of a processor provide information which describes multiple set-wise partitions of a cache. A second one or more registers of the processor provides additional information which describes multiple way-wise partitions of the cache. A virtual cache is defined as that region of the cache which is both in a particular set-wise partition, and in a particular way-wise partition. In another embodiment, a cache agent of the processor performs operations, based on the set-wise partitioning and the way-wise partitioning, to determine a mapping of one address—which is provided in a memory access request, and which indicates a location in one virtual cache—to another address which indicates another location in a different virtual cache.

Two-stage cache partitioning

A fabric controller to provide a coherent accelerator fabric, including: a host interconnect to communicatively couple to a host device; a memory interconnect to communicatively couple to an accelerator memory; an accelerator interconnect to communicatively couple to an accelerator having a last-level cache (LLC); and an LLC controller configured to provide a bias check for memory access operations.

Bias-based coherency in an interconnect fabric

A fabric controller is provided for a coherent accelerator fabric. The coherent accelerator fabric includes a host interconnect, a memory interconnect, and an accelerator interconnect. The host interconnect communicatively couples to a host device. The memory interconnect communicatively couples to an accelerator memory. The accelerator interconnect communicatively couples to an accelerator having a last-level cache (LLC). An LLC controller is provided that is configured to provide a bias check for memory access operations on the fabric.

Growing community of inventors

Sunnyvale, CA, United States of America

Ritu Gupta