Qualcomm Incorporated

Ritu Chaba

Nan Chen

Sei Seung Yoon

Chirag Gulati

Changho Jung

Arun Babu Pallerla

Rakesh Kumar Sinha

Stanley Seungchul Song

Ping Liu

Choh Fei Yeap

Zhongze Wang

Chulmin Jung

Niladri Mojumder

Keejong Kim

Hari Rao

Zhiqin Chen

Mehdi Hamidi Sani

Dongkyu Park

Balachander Ganesan

Lakshmikantha Holla Vakwadi

Naishad Parikh

Bipin Duggal

Mohamed H Abu Rahma

Niladri Narayan Mojumder

A memory is provided that is configured to practice both a conventional normal read operation and also a burst mode read operation. During the normal read operation, the memory pre-charges the bit lines in a group of multiplexed columns. Each column has a sense amplifier that latches a bit decision for the column during the normal read operation. If a subsequent read operation addresses the same group of multiplexed columns, the memory invokes the burst-mode read operation during which the bit lines are not pre-charged.

SRAM with burst mode operation

An apparatus including a memory subsystem. The memory subsystem includes a data input and a clock input. The apparatus also includes a variable delay circuit coupled to one of the data input or the clock input. Additionally, the apparatus includes a controller coupled to the variable delay circuit. The controller is configured to dynamically control the delay of the variable delay circuit. The controller may adjust the delay of the variable delay circuit based on at least one of timing data for a memory subsystem design of the memory subsystem, timing data for the memory subsystem, a voltage applied to the memory subsystem, or a temperature of the memory subsystem.

Memory hold margin characterization and correction circuit

A method and apparatus for writing data to a memory device are provided that do not change the precharge states for a bit line pair in a current write cycle if the current data bit is unchanged from the preceding write cycle.

Intelligent bit line precharge for improved dynamic power

A sense amplifier and method thereof are provided. The sense amplifier includes first and second transistors coupled to first and second bit lines, respectively. The first and second transistors are configured to connect the first and second bit lines to a differential amplifier during a first state (e.g., when a differential voltage is present on the first and second bit lines and prior to a sense signal transition) and to isolate the first and second bit lines from the differential amplifier during a second state (e.g., after the sense signal transition). The sense amplifier further includes a third transistor configured to deactivate the differential amplifier during the first state and configured to activate the differential amplifier during the second state.

Dual sensing current latched sense amplifier

An apparatus includes a first metal layer coupled to a bit cell. The apparatus also includes a third metal layer including a write word line that is coupled to the bit cell. The apparatus further includes a second metal layer between the first metal layer and the third metal layer. The second metal layer includes two read word lines coupled to the bit cell.

Metal layers for a three-port bit cell

Memory devices and methods of reducing leakage current therein are disclosed. The memory device includes a memory core array including a plurality of bitlines, and peripheral logic configured to interface with the memory core array. The memory device further includes a footswitch configured to isolate the peripheral logic from a ground voltage, and a headswitch configured to isolate a precharge current path from the plurality of bit lines of the memory core array. Leakage current within the memory device may be reduced via the isolation provided by the footswitch and the headswitch.

Reducing leakage current in a memory device

A bit line and word line tracking circuit is provided that accounts for the power-supply-voltage-dependent delays in a memory having a logic power domain powered by a logic power supply voltage and a memory power domain powered by a memory power supply voltage.

Word line and bit line tracking across diverse power domains

A method of operating an apparatus in a functional mode and an ATPG scan mode and an apparatus for use in a functional mode and an ATPG scan mode are provided. The apparatus includes a set of latches including a first latch and a second latch. The first latch is operated as a master latch and the second latch is operated as a master latch in the functional mode. The first latch is operated as a master latch of a flip-flop and the second latch is operated as a slave latch of the flip-flop in the ATPG scan mode. In one configuration, the apparatus includes a plurality of latches including at least the first and second latches, an output of each of the latches is coupled to a digital circuit, the apparatus includes a plurality of functional inputs, and each of the functional inputs is input to the digital circuit.

Reconfigurable memory interface circuit to support a built-in memory scan chain

Disclosed are various apparatuses and methods for a memory with a multiple word line design. A memory timing circuit may include a dummy word line including a first portion and a second portion and further including capacitative loading that is lumped in the second portion of the dummy word line, a first transistor connected to the first portion of the dummy word line and configured to charge the dummy word line, and a second transistor connected to the second portion of the dummy word line and configured to discharge the dummy word line. A method may include charging a dummy word line using a first transistor, and discharging the dummy word line using a second transistor, wherein the dummy word line includes a first portion and a second portion and further includes capacitative loading that is lumped in the second portion of the dummy word line.

Memory timing circuit

A memory circuit is provided comprising a plurality of bit cells coupled to a bit line that permits accessing information from each of the plurality of bit cells. A sense inverter is coupled to an output of the bit line. A keeper circuit has an output coupled to the bit line to compensate for current leakage from the plurality of bit cells. The keeper circuit may comprise an n-channel metal-oxide-silicon (NMOS) transistor in series with a p-channel metal-oxide-silicon (PMOS) transistor.

Weak keeper circuit for memory device

An integrated circuit includes one or more bit cells, a word line coupled to the one or more bit cells, and a dummy word line arranged with the word line to have a capacitance therebetween. The capacitance provides a voltage boost or reduction of the word line to assist read and write operations.

Read/write assist for memories

Disclosed are various apparatuses and methods for a memory with a multiple read word line design. A memory may include a plurality of bit cells arranged in a row, a first read word line connected to a first subset of the plurality of bit cells, and a second read word line connected to a second subset of the plurality of bit cells, wherein the first and second subsets are located in the same row of bit cells. A method may include asserting, during a first read operation, a first read word line connected to a first subset of a plurality of bit cells arranged in a row of bit cells, and asserting, during a second read operation, a second read word line connected to a second subset of the plurality of bit cells, wherein the first and second subsets are located in the same row of bit cells.

Growing community of inventors

San Diego, CA, United States of America

Ritu Chaba