Texas Instruments Corporation

Rittu Kulwant Sachdev

Debapriya Sahu

Gireesh Rajendran

Karthik Subburaj

Indu Prathapan

Rakesh Kumar

Apu Sivadas

Krishnaswamy Thiagarajan

Ashish Lachhwani

Shailesh Joshi

Karan Singh Bhatia

Pranav Sinha

Mayank Kumar Singh

A phase-locked loop (PLL) device includes: 1) a detector configured to output an error signal to indicate a phase offset between a feedback clock signal and a reference clock signal; 2) a charge pump coupled to the detector and configured to output a charge pump signal based on the error signal; 3) an integrator with a feedback path, an input node, a reference node, and an output node, wherein the input node is coupled to the charge pump and receives the charge pump signal; 4) a voltage-controlled oscillator (VCO) coupled to the output node of the integrator via a resistor; and 5) a feedforward circuit coupled directly to the detector and configured to apply an averaged version of the error signal to correct a voltage level received by the VCO.

Phase-locked loop (PLL) with direct feedforward circuit

A device comprises a digital ramp generator, an oscillator, a power amplifier, a low-noise amplifier (LNA), a mixer, and an intermediate frequency amplifier (IFA). The oscillator generates a chirp signal based on an output from the digital ramp generator. The power amplifier receives the chirp signal and outputs an amplified chirp signal to a transmitter antenna. The LNA receives a reflected chirp signal from a receiver antenna. The mixer receives output of the LNA and combines it with the chirp signal from the oscillator. The IFA receives the mixer output signal and includes a configurable high-pass filter, which has a first cutoff frequency during a first portion of the chirp signal and a second cutoff frequency during a second portion of the chirp signal. In some implementations, the first cutoff frequency is chosen based on a frequency of a blocker signal introduced by couplings between the transmitter and receiver antennas.

Intermediate frequency amplifier with a configurable high-pass filter

An integrated circuit device is provided. In some examples, the integrated circuit device includes a first re-timer configured to receive a reference clock signal and a voltage controlled oscillator (VCO) output signal, and the first re-timer is configured to provide a first re-timed clock signal in response to the reference clock signal and the VCO output signal. A multiplexer receives the first re-timed clock signal and provides a feedback clock signal. A phase frequency detector receives the feedback clock signal and the reference clock signal and provides an error signal in response to the feedback clock signal and the reference clock signal. A VCO receives a voltage signal based on the error signal, and the VCO is configured to provide the VCO output signal in response to the voltage signal.

Low-power fractional analog PLL without feedback divider

A circuit for sharing Tx/Rx ports of a CMOS based time multiplexed transceiver includes a Low Noise Amplifier (LNA) and a Power amplifier (PA), and deploys a single RF choke shared between the LNA and PA. The circuit selectively functions as a PA cascode or a LNA input device. In one form the circuit uses MOS transistors configured for use in one of Blue tooth, WLAN and TDMA applications, taking advantage of source-drain symmetry of the MOS transistors. The circuit may include a DC path and be used in WLAN applications, wherein the sharing of the single choke is enabled by one switch in the DC path. As described, the single RF choke is disposed outside of the LNA and the PA. The circuit supports high out powers and causes reduced signal loss due to just one LC tank as opposed to two LC tanks present in the prior art.

Technique for sharing transmit and receive ports of a CMOS based transceiver

A low-power receiver front-end includes a transconductance amplifier that produces a single-ended current signal in response to a single-ended voltage signal. An output of the transconductance amplifier is provided to an LC tuned circuit. At resonance, the LC tuned circuit generates a differential current signal in response to the single-ended current signal. Single-ended current signals corresponding to the resonant frequency of the LC tuned circuit are converted into differential signals. Further, the LC tuned circuit amplifies the differential current signals by an associated quality factor. Further, a mixer is coupled to an output of the LC tuned circuit. The mixer generates IF signals in response to the differential current signals.

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Bengaluru, India

Rittu Kulwant Sachdev