Mediatek Singapore Pte. Ltd.

Ritesh Garg

Chetan Deshpande

Gajanan Sahebrao Jedhe

Gaurang Prabhakar Narvekar

Yi-Wei Chen

Sushil Kumar

A content addressable memory (CAM) device includes multiple CAM sub-banks Each CAM sub-bank includes an array of CAM cells arranged in rows and columns and partitioned into a first stage and a second stage along a column dimension. Each CAM sub-bank further includes first-stage match lines (MLs), first-stage search line (SL) pairs, second-stage MLs, and second-stage SL pairs. Each second-stage SL pair is coupled to a column of CAM cells in the second stage and is gated by an SL enable (SL_EN signal). Each CAM sub-bank further includes a circuit operative to receive all of the first-stage MLs as input and de-assert the SL_EN signal when none of the first-stage MLs indicate a match. De-assertion of the SL_EN signal blocks a second portion search key from being provided to the second-stage SL pairs.

Dynamically gated search lines for low-power multi-stage content addressable memory

Ternary content-addressable memory (TCAM) devices are described. The TCAMs described herein are designed to perform write operations—including data writes and mask writes—in a single clock cycle. For example, data input is written in a row of the TCAM during the first portion of a clock cycle, and a mask is written in another row of the TCAM during the second portion of the clock cycle, for example immediately after or after a programmable delay from the data write. In one implementation, a first bus is used both for data write and key search operations, and a second bus is used both for mask write and search masking operations. In another implementation, a first bus is used both for data write and key search operations, a second bus is used for mask write operations, and a third bus is used for search masking operations.

Methods for writing ternary content addressable memory devices

A ternary content addressable memory (TCAM) device comprising an input interface having a first input for receiving first data and a second input for receiving second data; and a memory configured to write the first data into an address selected row of the memory at the same time that a comparison is performed between the second data and at least one other row of the memory different from the address selected row. More particularly, the input interface may further have a third input for receiving a search enable signal and a fourth input for receiving a write enable signal, wherein the memory is configured to write the first data and perform the comparison in response to assertion of the search enable signal at the same time as assertion of the write enable signal. An associated method is also provided.

Simultaneous write and search operation in a content addressable memory

Ternary content-addressable memory (TCAM) devices are described. The TCAMs described herein are designed to perform write operations&#x2014;including data writes and mask writes&#x2014;in a single clock cycle. For example, data input is written in a row of the TCAM during the first portion of a clock cycle, and a mask is written in another row of the TCAM during the second portion of the clock cycle. In one implementation, a first bus is used both for data write and key search operations, and a second bus is used both for mask write and search masking operations. In another implementation, a first bus is used both for data write and key search operations, a second bus is used for mask write operations, and a third bus is used for search masking operations.

Multi-stage content addressable memory devices are described. Some embodiments relate to memory devices including a plurality of rows of memory cells, multiple match lines and multiple pre-charge circuits. A first row of the plurality of rows includes a first segment and a second segment. The first segment may include a first subset of the memory cells of the first row and the second segment may include a second subset of the memory cells of the first row. The first match line is coupled to the memory cells of the first subset, and the second match line is coupled to the memory cells of the second subset. The first pre-charge circuit is configured to pre-charge the first match line to a first pre-charge voltage, and the second pre-charge circuit is configured to pre-charge the second match line to a second pre-charge voltage different from (e.g., greater than) the first pre-charge voltage.

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San Jose, CA, United States of America

Ritesh Garg