Stmicroelectronics S.r.l.

Stmicroelectronics International N.v.

Rita Zappa

Danilo Rimondi

Carolina Selva

Cosimo Torelli

Stefano Corbani

Giulio Ricotti

Chirag Gulati

Aldo Romani

Jitendra Dasani

Donatella Brambilla

Giovanni Mastrodomenico

Matteo Pizzotti

Michele Dini

An electronic converter has first and second input terminals, first and second output terminals, a current regulator circuit arranged between the first input terminal and an intermediate node, and input capacitor arranged between the intermediate node and the second input terminal, and an output capacitor. A control circuit block is configured to sense an input voltage, compare the regulated voltage to a reference value and generate a first signal, compare the input voltage to a lower threshold and an upper threshold and generate a second signal, switch the electronic converter between an active mode and an idle mode as a function of the first signal, and switch the electronic converter between a recharge phase and a switching phase as a function of the second signal when the electronic converter is in the active mode.

Electronic converter and method of operating an electronic converter

An embodiment of a method for detecting permanent faults of an address decoder of an electronic memory device including a memory block formed by a plurality of memory cells, including the steps of: selecting an address, which identifies a selected set of memory cells; writing at the selected address a code word generated on the basis of an information word, of the selected address, and of an error-correction code; and then detecting an error within a word stored at the selected address. The method moreover includes the steps of: selecting a set of excitation addresses; writing a test word at the selected address, and then writing an excitation word at each excitation address; and next comparing the test word with a new word stored at the selected address.

Method for detecting permanent faults of an address decoder of an electronic memory device

An embodiment of a memory device includes a plurality of memory cells; each memory cell includes a latch adapted to store an information bit. Said latch includes a first logic gate including a first input terminal and a first output terminal and a second logic gate including a second input terminal and a second output terminal. Said first input terminal is connected to said second output terminal and said first output terminal is connected to said second input terminal. The memory device further includes reading and writing means adapted to perform a read operation or a write operation of the information bit. Said first logic gate includes a pull-up branch coupled between a terminal for providing a supply voltage and the first output terminal, and a pull-down branch coupled between the first output terminal and a terminal for providing a reference voltage. Said second logic gate includes a pull-up branch coupled between a terminal for providing the supply voltage and the second output terminal, and a pull-down branch coupled between the second output terminal and a terminal for providing the reference voltage. Said memory device includes variation means adapted to selectively vary a gain factor of at least one between the pull-down branch and the pull-up branch of said first logic gate and second logic gate depending on the operation performed by the reading and writing means.

Adjustable impedance SRAM memory device

A circuit for detecting a single bit upset in a dynamic logic circuit includes a latch circuit having an input for receiving a reset signal, and an output for providing a flag output signal, the latch circuit being clocked by a first clock signal, a first transistor having a drain coupled to the output of the latch circuit, a gate for receiving a second clock signal, and a source, and a second transistor having a drain coupled to the source of the first transistor, a gate for receiving a third clock signal, and a source coupled to ground.

Detection of single bit upset at dynamic logic due to soft error in real time

A method is for making an integrated circuit with built-in self-test. The method includes forming at least one nonvolatile read only memory (ROM) to store ROM code and forming a logic self-test circuit to verify a correct functioning of the at least one nonvolatile ROM. Moreover, the method includes defining, in the logic self-test circuit, a logic self-test core to process the ROM code and to generate a flag based upon a control signature and defining, in the logic self-test circuit, a nonvolatile storage block, coupled to the logic self-test core, to store the control signature. Furthermore, the method includes writing the ROM code to the at least one nonvolatile ROM and writing the control signature to the nonvolatile storage block, during a same fabrication step.

Process and system for the verification of correct functioning of an on-chip memory

A self diagnosis (BISD) device for a random memory array, preferably integrated with the random access memory, executes a certain number of predefined test algorithms and identifies addresses of faulty locations. The BISD device recognizes certain fail patterns of interest and generates bit-strings corresponding to them. In practice, the BISD device may diagnose memory arrays and allow the identification of defects in the production process that affect a new technology during its learning phase, thus accelerating its maturation.

Built-in self diagnosis device for a random access memory and method of diagnosing a random access

A built-in self-test and self-repair structure (BISR) of memory arrays embedded in an integrated device includes at least a test block (BIST) programmable to execute on a respective memory array of the device any of a certain number of test algorithms, and a self-repair block that includes a column address generator processing the faulty address information for allocating redundant resources of the tested memory array. The BISR may further include a redundancy register on which final redundancy information is loaded at each power-on of the device and control logic for managing data transfer from external circuitry to the built-in self-test and self-repair structure (BISR) and vice versa. The BIST structure serves any number of embedded memory arrays even of different types and sizes.

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Milan, Italy

Rita Zappa