Intel Corporation

Rita D Gupta

Francesc Guim Bernat

Karthik Kumar

Dimitrios Ziakas

Thomas Willhalm

Mark A Schmisseur

Alexander Bachmutsky

Anand K Enamandram

Robert A Branch

Kerry Vander Kamp

Barun Bikash Paul

Suresh Thirumandas

An apparatus comprising a first memory interface of a first type to couple to at least one first memory device; a second memory interface of a second type to couple to at least one second memory device; and circuitry to interleave memory requests targeting contiguous memory addresses among the at least one first memory device and the at least one second memory device.

Interleaving of heterogeneous memory targets

The apparatus of a disaggregated memory architecture (DMA) including a shared memory and multiple nodes is programmable by a primary node of the DMA. The primary node executes a programming agent to, prior to memory access requests to the shared memory, cause a programming of register entries of one or more registers of a memory pooling circuitry (MPC) with information to be used by a decoder of the MPC to translate host physical addresses (HPA) of memory access requests of the nodes to local memory addresses (LMAs). The LMAs are to be processed by one or more memory controllers (MCs) based on MC memory regions in each of the one or more MCs, the MC memory regions having a predetermined memory size granularity. At least some of the LMAs map to non-contiguous memory regions of the shared memory and of the one or more MCs.

Software driven dynamic memory allocation and address mapping for disaggregated memory pool

An embodiment of an electronic apparatus may comprise one or more substrates, and a controller coupled to the one or more substrates, the controller to allocate a first secure portion of a pooled memory to a first instantiation of an application on a first node, and circuitry coupled to the one or more substrates and the controller, the circuitry to provide a failover interface for a second instantiation of the application on a second node to access the first secure portion of the pooled memory in the event of a failure of the first node. Other embodiments are disclosed and claimed.

Failover for pooled memory

In one embodiment, an apparatus includes an interface to couple a plurality of devices of a system, the interface to enable communication according to a Compute Express Link (CXL) protocol, and a power management circuit coupled to the interface. The power management circuit may: receive, from a first device of the plurality of devices, a request according to the CXL protocol for updated power credits; identify at least one other device of the plurality of devices to provide at least some of the updated power credits; and communicate with the first device and the at least one other device to enable the first device to increase power consumption according to the at least some of the updated power credits. Other embodiments are described and claimed.

System, apparatus and methods for power communications according to a CXL power protocol

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Cedar Park, TX, United States of America

Rita D Gupta