Nvidia Corporation

Rishkul Kulkarni

Konstantinos Kyriakopoulos

Jack H Choquette

Olivier Giroux

Ronny Krashinsky

Harold Carter Edwards

Aditya Avinash Atluri

Sean Jeffrey Treichler

Gary M Tarolli

Mark William Stephenson

Ajay Sudarshan Tirumala

Andrew Robert Kerr

Ze Long

Daniel Robert Johnson

Ram Rangan

Alan Kaatz

Kyrylo Perelygin

Apoorv Parle

Girish Bharambe

Praveen Kaushik

Maciej Piotr Tyrlik

Peter Nelson

Gokul Ramaswamy Hirisave Chandra Shekhara

Edward H Gornish

Sana Damani

James Player

Cris Cecka

Aman Arora

Yashwardhan Narawane

Divya Shanmughan

Vikram Dhar

Ankita Upreti

Balaji Krishna Yugandhar Atukuri

Carter Edwards

Bageshri Sathe

David Allan Berson

Haicheng Wu

Vijay Thakkar

Cody Addison

Apparatuses, systems, and techniques to cause to cause one or more first storage address sizes to be converted into one or more second storage address sizes. In at least one embodiment, one or more circuits are to perform an application programming interface (API) to cause one or more first storage address sizes to be converted to one or more second storage address sizes based, at least in part, on one or more identifiers of one or more physical storage locations corresponding to either of the one or more first storage address sizes or the one or more second storage address sizes.

Address size conversion via application programming interface

Apparatuses, systems, and techniques to adapt instructions in a SIMT architecture for execution on serial execution units. In at least one embodiment, a set of one or more threads is selected from a group of active threads associated with an instruction and the instruction is executed for the set of one or more threads on a serial execution unit.

Scalarization of instructions for SIMT architectures

Various embodiments include a parallel processing computer system that enables parallel instances of a program to synchronize at disparate addresses in memory. When the parallel program instances need to exchange data, the program instances synchronize based on a mask that identifies the program instances that are synchronizing. As each program instance reaches the point of synchronization, the program instance blocks and waits for all other program instances to reach the point of synchronization. When all program instances have reached the point of synchronization, at least one program instance executes a synchronous operation to exchange data. The program instances then continue execution at respective and disparate return addresses.

Techniques for efficiently synchronizing multiple program threads

Apparatuses, systems, and techniques to perform computational operations in response to one or more compute uniform device architecture (CUDA) programs. In at least one embodiment, one or more computational operations are to cause one or more other computational operations to wait until a portion of matrix multiply-accumulate (MMA) operations have been performed.

Application programming interface to wait on matrix multiply-accumulate

Warp sharding techniques to switch execution between divergent shards on instructions that trigger a long stall, thereby interleaving execution between diverged threads within a warp instead of across warps. The technique may be applied to mitigate pipeline stalls in applications with low warp occupancy and high divergence. Warp data cache locality may also be improved by concentrating memory accesses within a warp rather than spreading them across warps.

Techniques for divergent thread group execution scheduling

Growing community of inventors

Austin, TX, United States of America

Rishkul Kulkarni