Oracle International Corporation

Arm Limited

Rishabh Jain

Erik Schlanger

David Allen Brown

Michael Alexander Duller

Sam Idicula

David Joseph Hawkins

Ashok Kumar Tummala

Christopher Joseph Daniels

Jamshed Jalal

Tushar P Ringe

Daniel Fowler

Sai Kumar Marri

David Avraham Brown

Mark David Werkheiser

Kishore Kumar Jagadeesha

Apurva Patel

Devi Sravanthi Yalamarthy

Surabhi Garg

Fnu Parshant

Erik M Schlanger

David A Brown

A hardware-assisted Distributed Memory System may include software configurable shared memory regions in the local memory of each of multiple processor cores. Accesses to these shared memory regions may be made through a network of on-chip atomic transaction engine (ATE) instances, one per core, over a private interconnect matrix that connects them together. For example, each ATE instance may issue Remote Procedure Calls (RPCs), with or without responses, to an ATE instance associated with a remote processor core in order to perform operations that target memory locations controlled by the remote processor core. Each ATE instance may process RPCs (atomically) that are received from other ATE instances or that are generated locally. For some operation types, an ATE instance may execute the operations identified in the RPCs itself using dedicated hardware. For other operation types, the ATE instance may interrupt its local processor core to perform the operations.

On-chip atomic transaction engine

A mechanism for error containment in a data processing system includes receiving a transaction request at a gateway between a host and a device, allocating an entry for the request in a local request tracker of the gateway and sending a link request, to a port of the gateway. In response to an isolation trigger, the port is moved into isolation by completing in-process requests with entries in the tracker and locking the entries. On receiving a response to an in-process request while the port is in isolation, the response is dropped, the associated entry is unlocked, and allocation of the entry is enabled. A completion response is sent to the requester without dispatching a new link request to the port. When requests are completed, the system is quiesced, locked entries are unlocked, and the port is moved out of isolation.

Traffic isolation at a chip-to-chip gateway of a data processing system

The present disclosure advantageously provides a method and system for transferring data over a chip-to-chip interconnect (CCI). At a request node of a coherent interconnect (CHI) of a first chip, receiving at least one peripheral component interface express (PCIe) transaction from a PCIe master device, the PCIe transaction including a stream identifier; selecting a CCI port of the CHI of the first chip based on the stream identifier of the PCIe transaction; and sending the PCIe transaction to the selected CCI port.

CCIX port management for PCI express traffic

The present disclosure advantageously provides a method and system for transferring data over at least one interconnect. A request node, coupled to an interconnect, receives a first write burst from a first device over a first connection, divides the first write burst into an ordered sequence of smaller write requests based on the size of the first write burst, and sends the ordered sequence of write requests to a home node coupled to the interconnect. The home node generates an ordered sequence of write transactions based on the ordered sequence of write requests, and sends the ordered sequence of write transactions to a write combiner coupled to the home node. The write combiner combines the ordered sequence of write transactions into a second write burst that is the same size as the first write burst, and sends the second write burst to a second device over a second connection.

Message protocol for a data processing system

Techniques are provided for configuring and operating hardware to sustain real-time hashing throughput. In an embodiment, during a first set of clock cycles, a particular amount of data items of a first data column are transferred into multiple hash lanes. During a second set of clock cycles, the same particular amount of data items of a second data column are transferred into the hash lanes. The transferred data items of the first and second data columns are then processed to calculate a set of hash values. When combined with techniques such as pipelining and horizontal scaling, the loading, hashing, and other processing occur in real time at the full speed of the underlying data path. For example, hashing throughput may sustainably equal or exceed the throughput of main memory.

Dynamically configurable high performance database-aware hash engine

Distributed shared memory using interconnected atomic transaction engines at respective memory interfaces

Techniques are described herein for efficient movement of data from a source memory to a destination memory. In an embodiment, in response to a particular memory location being pushed into a first register within a first register space, the first set of electronic circuits accesses a descriptor stored at the particular memory location. The descriptor indicates a width of a column of tabular data, a number of rows of tabular data, and one or more tabular data manipulation operations to perform on the column of tabular data. The descriptor also indicates a source memory location for accessing the tabular data and a destination memory location for storing data manipulation result from performing the one or more data manipulation operations on the tabular data. Based on the descriptor, the first set of electronic circuits determines control information indicating that the one or more data manipulation operations are to be performed on the tabular data and transmits the control information, using a hardware data channel, to a second set of electronic circuits to perform the one or more operations. Based on the control information, the second set of electronic circuits retrieve the tabular data from source memory location and apply the one or more data manipulation operations to generate the data manipulation result. The second set of electronic circuits cause the data manipulation result to be stored at the destination memory location. Among the data manipulation operations that can be described are a bit vector based gather operation. The second set of electronic circuits determine a row count, which is generated efficiently by the second set of electronic circuits and is used to perform a gather operation and other types of data manipulation operations more efficiently.

Bit vector gather row count calculation and handling in direct memory access engine

Techniques are provided for exchanging dedicated hardware signals to manage a first-in first-out (FIFO). In an embodiment, a first processor initiates content transfer into the FIFO. The first processor activates a first hardware signal that is reserved for indicating that content resides within the FIFO. A second processor activates a second hardware signal that is reserved for indicating that content is accepted. The second hardware signal causes the first hardware signal to be deactivated. This exchange of hardware signals demarcates a FIFO transaction, which is mediated by interface circuitry of the FIFO.

Processor core to coprocessor interface with FIFO semantics

Techniques are provided for improving the performance of a constellation of coprocessors by hardware support for asynchronous events. In an embodiment, a coprocessor receives an event descriptor that identifies an event and a logic. The coprocessor processes the event descriptor to configure the coprocessor to detect whether the event has been received. Eventually a device, such as a CPU or another coprocessor, sends the event. The coprocessor detects that it has received the event. In response to detecting the event, the coprocessor performs the logic.

Multi-purpose events for notification and sequence control in multi-core processor systems

Techniques provide for hardware accelerated data movement between main memory and an on-chip data movement system that comprises multiple core processors that operate on the tabular data. The tabular data is moved to or from the scratch pad memories of the core processors. While the data is in-flight, the data may be manipulated by data manipulation operations. The data movement system includes multiple data movement engines, each dedicated to moving and transforming tabular data from main memory data to a subset of the core processors. Each data movement engine is coupled to an internal memory that stores data (e.g. a bit vector) that dictates how data manipulation operations are performed on tabular data moved from a main memory to the memories of a core processor, or to and from other memories. The internal memory of each data movement engine is private to the data movement engine. Tabular data is efficiently copied between internal memories of the data movement system via a copy ring that is coupled to the internal memories of the data movement system and/or is coupled to a data movement engine. Also, a data movement engine internally broadcasts data to other data movement engines, which then transfer the data to respective core processors. Partitioning may also be performed by the hardware of the data movement system. Techniques are used to partition data 'in flight'. The data movement system also generates a column of row identifiers (RIDs). A row identifier is a number treated as identifying a row or element's position within a column. Row identifiers each identifying a row in column are also generated.

Growing community of inventors

Austin, TX, United States of America

Rishabh Jain