California Institute of Technology

Risaku Toda

Harish M Manohara

Goutam Chattopadhyay

Choonsup Lee

Imran Mehdi

Cecile D Jung-Kubiak

Robert H Lin

John J Gill

Ken B Cooper

Alejandro Peralta

Theodore J Reck

Jose V Siles

Bertrand Thomas

Michael J Bronikowski

Linda Y Del Castillo

Edward M Luong

Rakesh Murthy

Valerie Kristof

A silicon alignment pin is used to align successive layer of component made in semiconductor chips and/or metallic components to make easier the assembly of devices having a layered structure. The pin is made as a compressible structure which can be squeezed to reduce its outer diameter, have one end fit into a corresponding alignment pocket or cavity defined in a layer of material to be assembled into a layered structure, and then allowed to expand to produce an interference fit with the cavity. The other end can then be inserted into a corresponding cavity defined in a surface of a second layer of material that mates with the first layer. The two layers are in registry when the pin is mated to both. Multiple layers can be assembled to create a multilayer structure. Examples of such devices are presented.

Wafer-to-wafer alignment method

A silicon alignment pin is used to align successive layers of components made in semiconductor chips and/or metallic components to make easier the assembly of devices having a layered structure. The pin is made as a compressible structure which can be squeezed to reduce its outer diameter, have one end fit into a corresponding alignment pocket or cavity defined in a layer of material to be assembled into a layered structure, and then allowed to expand to produce an interference fit with the cavity. The other end can then be inserted into a corresponding cavity defined in a surface of a second layer of material that mates with the first layer. The two layers are in registry when the pin is mated to both. Multiple layers can be assembled to create a multilayer structure. Examples of such devices are presented.

Silicon alignment pins: an easy way to realize a wafer-to-wafer alignment

Systems and methods in accordance with embodiments of the invention proficiently produce carbon nanotube-based vacuum electronic devices. In one embodiment a method of fabricating a carbon nanotube-based vacuum electronic device includes: growing carbon nanotubes onto a substrate to form a cathode; assembling a stack that includes the cathode, an anode, and a first layer that includes an alignment slot; disposing a microsphere partially into the alignment slot during the assembling of the stack such that the microsphere protrudes from the alignment slot and can thereby separate the first layer from an adjacent layer; and encasing the stack in a vacuum sealed container.

Systems and methods for fabricating carbon nanotube-based vacuum electronic devices

Systems and methods in accordance with embodiments of the invention implement carbon nanotube-based field emitters. In one embodiment, a method of fabricating a carbon nanotube field emitter includes: patterning a substrate with a catalyst, where the substrate has thereon disposed a diffusion barrier layer; growing a plurality of carbon nanotubes on at least a portion of the patterned catalyst; and heating the substrate to an extent where it begins to soften such that at least a portion of at least one carbon nanotube becomes enveloped by the softened substrate.

Systems and methods for implementing robust carbon nanotube-based field emitters

A carbon nanotube field emission device with overhanging gate fabricated by a double silicon-on-insulator process. Other embodiments are described and claimed.

Method for manufacturing a carbon nanotube field emission device with overhanging gate

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Glendale, CA, United States of America

Risaku Toda