Intel Corporation

Ripan Das

Nikhil Gupta

Krishnakanth Venkata Sistla

Ankush Varma

Vivek Garg

Ian M Steiner

Nagasubramanian Gurumoorthy

John Joseph Browne

Chris MacNamara

Vasudevan Srinivasan

Venkatesh Ramamurthy

Corey D Gough

William Johnson Bowhill

Sujal A Vora

David P Lerner

Joseph M Sullivan

Andrew J Herdrich

Dean A Mulla

Andy Keates

Nazar Syed Haider

Yogesh Bansal

Adwait Purandare

Suresh Chemudupati

Aman Sewani

Eric Dehaemer

Nilanjan Palit

Rupal Parikh

Pavithra Sampath

Wenhui Shu

Ujjwal Gupta

Stanley Chen

Nikethan Shivanand Baligar

Stephen Wang

Dorit Shapira

Shruthi Venugopal

Phani Kumar Kandula

Michael Tulanowski

Timothy Yee-Kwong Kam

Stephen Paul Haake

Dianjun Sun

A processing device includes a plurality of processing cores, a control register, associated with a first processing core of the plurality of processing cores, to store a first base clock frequency value at which the first processing core is to run, and a power management circuit to receive a base clock frequency request comprising a second base clock frequency value, store the second base clock frequency value in the control register to cause the first processing core to run at the second base clock frequency value, and expose the second base clock frequency value on a hardware interface associated with the power management circuit.

Configuration of base clock frequency of processor based on usage parameters

Hierarchical Power Management (HPM) architecture considers the limits of scaling on a power management controller, the autonomy at each die, and provides a unified view of the package to a platform. At a simplest level, HPM architecture has a supervisor and one or more supervisee power management units (PMUs) that communicate via at least two different communication fabrics. Each PMU can behave as a supervisor for a number of supervisee PMUs in a particular domain. HPM addresses these needs for products that comprise a collection of dice with varying levels of power and thermal management capabilities and needs. HPM serves as a unified mechanism than can span collection of dice of varying capability and function, which together form a traditional system-on-chip (SoC). HPM provides a basis for managing power and thermals across a diverse set of dice.

Hierarchical power management apparatus and method

Examples include a computing system for receiving memory class of service parameters; setting performance monitoring configuration parameters, based at least in part on the memory class of service parameters, for use by a performance monitor of a memory controller to generate performance monitoring statistics by monitoring performance of one or more workloads by a plurality of processor cores based at least in part on the performance monitoring configuration parameters; receiving the performance monitoring statistics from the performance monitor; and generating, based at least in part on the performance monitoring statistics, a plurality of memory bandwidth settings to be applied by a memory bandwidth allocator to the plurality of processor cores to dynamically adjust priorities of memory bandwidth allocated for the one or more workloads to be processed by the plurality of processor cores.

Dynamic control of memory bandwidth allocation for a processor

A method and system for applying a multi-rate charge to a battery are included herein. The method includes detecting a plurality of predetermined electrical measurements and a plurality of predetermined charge currents. The method also includes detecting an electrical measurement of the battery. Additionally, the method includes selecting a charge current from the plurality of predetermined charge currents to be applied to the battery based on the electrical measurement of the battery and the plurality of predetermined electrical measurements. Furthermore, the method includes applying the charge current to the battery. The method also includes detecting a plurality of subsequent electrical measurements of the battery. In addition, the method includes applying a plurality of subsequent charge currents to the battery based on the plurality of subsequent electrical measurements of the battery and the plurality of predetermined charge currents.

Charging a battery using a multi-rate charge

An apparatus is provided that includes a memory controller to provide a first on-die termination (ODT) signal and a second ODT signal, a memory channel, a first memory module to couple to the memory channel, and a second memory module to couple to the memory channel. The first memory module may include a first memory having a first ODT circuit to receive the first ODT signal, and a second memory having a second ODT circuit to receive the first ODT signal. The first ODT signal may disable the ODT circuit of the first memory when the first memory is to be ACTIVE.

Low power termination for memory modules

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Beaverton, OR, United States of America

Ripan Das