Stmicroelectronics S.r.l.

Other

Pmc-sierra Us, Inc.

IP Gem Group, LLC

Micron Technology Incorporated

Microchip Technology Inc.

Microsemi Storage Solutions (u.s.), Inc.

Microsemi Solutions (us), Inc.

Hynix Semiconductor Inc.

Sgs-thomson Microelectronics S.r.l.

Integrated Device Technology, Inc.

Rino Micheloni

Giovanni Campardo

Alessia Marelli

Luca Crippa

Roberto Ravasio

Peter Onufryk

Christopher I W Norrie

Osama Khouri

Guido Torelli

Andrea Sacco

Ilaria Motta

Miriam Sangalli

Andrea Pierin

Giancarlo Ragone

Lorenzo Zuolo

Marco MacCarrone

Stefano Commodaro

Stefano Gregori

Salvatrice Scommegna

Angelo Bovino

Ihab Jaser

Matteo Zammattio

Aldo Losavio

Donato Ferrario

Antonio Aldarese

Massimiliano Lunelli

Atsushi Ohba

Carla Maria Golla

Massimiliano Picca

Alessandro Manstretta

Marcello Carrera

Chiara Missiroli

Federico Pio

Paolo Giuseppe Cappelletti

Roberto Gastaldi

Amir Mosek

Alfonso Maurelli

Stefano Zanardi

Giulio Casagrande

Ignazio Martines

Jacopo Mulatti

Stephen Bates

Stefano Ghezzi

Maurizio Branchetti

Eran Kirzner

Guido Lomazzi

Ron Cohen

Sabina Mognoni

Valeria Intini

Vincenzo Altieri

Marco Roveda

Andrea Silvagni

Unnikrishnan Sivaraman Nair

Irene Babudri

Robert Scott Fryman

Dario Soltesz

Emilio Yero

Miram Sangalli

Mario De Matteis

Marco Capovilla

Khouri Osama

Sergio Coronini

Marco Scotti

Francesco Farina

A method includes storing configuration files of a Multi-Core Neural Network Inference (MCNNI) model having Independent Categorized-Core-Portions (ICCP). Each ICCP corresponds to one of a plurality of categories for each parameter. Some weighting values on each row of the weighting matrix of the MCNNI model have a nonzero value and some weighting values on each row have a value of zero. The configuration files are loaded into a neural network engine. The operation of the flash controller integrated circuit is monitored to identify a usage value corresponding to each of the parameters. A single neural network operation is performed using the usage values as input to generate output values. The output values of the ICCP that corresponds to the input usage values are identified and a TVSO value corresponding to the identified output values is identified. A read of a flash memory device is performed using the identified TVSO value.

Partitionable neural network for solid state drives

A method and apparatus for reading a flash memory device are disclosed. A Regression Neural Network (RNN) inference model is stored on a flash controller. The RNN inference model is configured for identifying at least one Threshold-Voltage-Shift Read-Error (TVS-RE) curve that identifies a number of errors as a function of Threshold Voltage Shift Offset (TVSO) values. The operation of a flash memory device is monitored to identify usage characteristic values. A neural network operation of the RNN inference model is performed to generate a TVS-RE curve corresponding to the usage characteristic values. The input for the neural network operation includes the usage characteristic values. A TVSO value is identified corresponding to a minimum value of the TVS-RE curve. A read of the flash memory device is performed using a threshold-voltage-shift read at the TVSO value.

Regression neural network for identifying threshold voltages to be used in reads of flash memory devices

A method for meeting quality of service (QoS) requirements in a flash controller that includes one or more instruction queues and a neural network engine. A configuration file for a QoS neural network is loaded into the neural network engine. A current command is received at the instruction queue(s). Feature values corresponding to commands in the instruction queue(s) are identified and are loaded into the neural network engine. A neural network operation of the QoS neural network is performed using as input the identified feature values to predict latency of the current command. The predicted latency is compared to a first latency threshold. When the predicted latency exceeds the first latency threshold one or more of the commands in the instruction queue(s) are modified. The commands are not modified when the predicted latency does not exceed the latency threshold. A next command in the instruction queue(s) is then performed.

Machine learning assisted quality of service (QoS) for solid state drives

A method for performing a read of a flash memory includes storing configuration files for a plurality of RRD-compensating RNNs. A current number of PE cycles for a flash memory are identified and TVSO values are identified corresponding to the current number of PE cycles. A current retention time and a current number of read disturbs for the flash memory are identified. The configuration file of the RRD-compensating RNN corresponding to the current number of PE cycles, the current retention time and current number of read disturbs is selected and is loaded into a neural network engine to form an RNN core in the neural network engine. A neural network operation of the RNN core is performed to predict RRD-compensated TVSO values. The input to the neural network operation includes the identified TVSO values. A read of the flash memory is performed using the predicted RRD-compensated TVSO values.

Method and apparatus for performing a read of a flash memory using predicted retention-and-read-disturb-compensated threshold voltage shift offset values

A method for outlier management at a flash controller includes testing a flash memory device to identify one or more outlier blocks of the flash memory device. Hyperparameters for a DNN are loaded into a training circuit of the flash controller. Test reads of the one or more outlier blocks are performed and a number of errors in the test reads is identified. The DNN is trained using a mini-batch training process and using the identified number of errors in the test reads and is tested to determine whether the trained DNN meets a training error threshold. The performing, the identifying, the training and the testing are repeated until the trained DNN meets the training error threshold to identify parameters of an outlier-block DNN. A neural network operation is performed using the identified parameters to predict a set of TVSO values. A read is performed using the set of predicted TVSO values.

Method and apparatus for outlier management

A method for reading a flash memory device includes storing configuration files of reliability-state Classification Neural Network (CNN) models and Regression Neural Network (RNN) inference models, and storing reliability-state tags corresponding to reliability states. The current number of P/E cycles is identified and a reliability-state CNN model is selected corresponding to the current number of P/E cycles. A neural network operation of the selected reliability-state CNN model is performed to identify a predicted reliability state. Corresponding reliability-state tags are identified and a corresponding RNN inference model is selected. A neural network operation of the selected RNN inference model is performed, using the reliability-state tags as input, to generate output indicating the shape of a threshold-voltage-shift read-error (TVS-RE) curve. Threshold Voltage Shift Offset (TVSO) values are identified corresponding to a minimum value of the TVS-RE curve and a read is performed using a threshold-voltage-shift read at the identified TVSO values.

Method and apparatus for reading a flash memory device

A method and apparatus for determining when actual wear of a flash memory device differs from a reliability state. Configuration files of a reliability-state classification neural network model are stored. The operation of a flash memory device is monitored to identify current physical characteristic values. A read of the flash memory device is performed to determine a number of errors. A neural network operation is performed using as input a set of threshold voltage shift offset values currently being used to perform reads of the flash memory device and the calculated number of errors, to identify a predicted reliability state. The identified current physical characteristic values are compared to corresponding tags associated with the predicted reliability state and a flag or other indication is stored when the comparison indicates that the identified current physical characteristic values do not correspond to the respective tags associated with the predicted reliability state.

Method and apparatus for determining when actual wear of a flash memory device differs from reliability states for the flash memory device

A method and associated system for randomizing data to be stored in a memory storage device including, receiving a plurality of data bytes to be randomized at a memory controller and written to a page of a memory storage device, wherein the page comprises a plurality of data sectors and wherein each of the plurality of data sectors are configured to store a plurality of data bytes, randomizing a first portion of the plurality of data bytes using a first randomizer initialized by a first seed to generate a first portion of randomized data bytes and randomizing a second portion of the plurality of data bytes using a second randomizer initialized by a second seed to generate a second portion of randomized data bytes, wherein the first seed is uncorrelated with the second seed.

System and method for randomizing data

A method and system for making error corrections on digital information coded as symbol sequences, for example digital information stored in electronic memory systems or transmitted from and to these systems is described, provides the 5 transmission of sequences incorporating a portion of error corrector code allowing the sequence which is more probably the original transmitted through the calculation of an error syndrome using a parity matrix to be restored when received. Advantageously according to embodiments of the invention, the error code incorporated in the original sequence belongs to a non Boolean group.

Method for performing error corrections of digital information codified as a symbol sequence

A nonvolatile memory system, a nonvolatile memory controller and a method for assuring retention are disclosed. The nonvolatile memory controller includes a retention monitor that stores test characteristics corresponding to a use case and determines, each time that a read of a codeword is performed, whether the number of errors in the codeword exceed a retention threshold. If the number of errors in the codeword exceed the retention threshold, the block containing the codeword is retired. The retention monitor performs retention tests during the operation of the memory controller and adjusts the retention threshold when the results of the retention tests indicate deviation from the test characteristics corresponding to a use case.

Nonvolatile memory system with retention monitor

A method for identifying log likelihood ratio (LLR) values includes programming codewords into nonvolatile memory devices in response to receiving host-requested write instructions and performing background reads of the programmed codewords in a block at a default threshold voltage, at one or more threshold voltage offset that is less than the default threshold voltage and at one or more threshold voltage offset that is greater than the default threshold voltage. One of the background reads is decoded to identify the stored codeword(s) and a set of LLR values is identified using the stored read results and the identified codeword(s). The process of performing background reads, storing, decoding and identifying is repeated to identify a set of LLR values for each block and further to identify updated sets of LLR values. Host-requested reads are performed and are decoded using LLR values from the updated set of LLR values corresponding to the block that was read.

Auto-learning log likelihood ratio

A nonvolatile memory system, a nonvolatile memory controller and a method for reducing latency of a memory controller are disclosed. The nonvolatile memory system includes a read circuit that performs background reads of an indicator page of each block to identify outlier blocks. A background reference positioning circuit performs background reads of representative pages of the outlier block at threshold voltage offsets to identify sets of updated threshold voltage offset values. Upon endurance events, retention timer events and read disturb events at a closed block background reads are performed of representative pages of the closed block at threshold voltage offsets to identify sets of updated threshold voltage offset values. When a usage characteristic meets one or more usage characteristic threshold, the read circuit performs subsequent host-requested reads of pages of blocks meeting the usage characteristic threshold using a threshold voltage shift read instruction and using the corresponding set of updated threshold voltage offset values.

Nonvolatile memory system with background reference positioning and local reference positioning

Methods and apparatus are disclosed for decoding low-density parity check (LDPC) encoded data using a parity check matrix having a plurality of layers. The apparatus includes a decoder having circuitry to decode, layer by layer, a LDPC codeword utilizing functional adjustments and an algorithmic approximation to belief propagation to provide an estimate of the LDPC codeword, the functional adjustments including layer specific parameters for at least two layers of the parity check matrix associated with the LDPC codeword.

Method and apparatus for layer-specific LDPC decoding

A nonvolatile memory system, a nonvolatile memory controller and a method for reducing latency of a memory controller are disclosed. Upon the occurrence of one or more of an endurance event, a retention timer event and a read disturb event at a closed block, a background reference positioning circuit performs background reads of representative pages of each page group of a closed block at offsets to each threshold voltage that is required for reading the representative pages of each page group of the closed block to identify a set of updated threshold voltage offset values for each page group of the closed block. When a usage characteristic is determined to meet a usage characteristic threshold, a read circuit performs subsequent host-requested reads using a threshold voltage shift read instruction and reads of pages of the closed block are performed using the set of updated threshold voltage offset values corresponding to the page group of the page being read.

Background reference positioning and local reference positioning using threshold voltage shift read

A nonvolatile memory controller and a method for erase suspend management are disclosed. The nonvolatile memory controller includes an erase suspend circuit configured for determining a pre-suspend time each time that an erase operation of the nonvolatile memory device is suspended and for determining whether an erase-suspend limit has been reached using the determined pre-suspend time. The erase suspend circuit is further configured for incrementing the number of program and erase cycles when the erase-suspend limit has been reached.

Nonvolatile memory controller and method for erase suspend management that increments the number of program and erase cycles after erase suspend

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Turate, Italy

Rino Micheloni