Applied Materials, Inc.

Rinat Shimshi

Youval Nehmadi

Vicky Svidenko

Alexander T Schwarm

Satish Sundar

Sekar Krishnasamy

Donald J Foldenauer

Mordechai Leska

Sundar Jawaharlal

Vijay Sakhare

Marvin L Freeman

Jeffery Hudgens

Ariel Ben-Porath

Jacob Joseph Orbon, Jr

Ofer Bokobza

Erez Ravid

Sundar Jawaharlah

Embodiments of the present invention provide methods and apparatuses for determining factors for design consideration in yield analysis of semiconductor fabrication. In one embodiment, a computer-implemented method for determining factors for design consideration in yield analysis of semiconductor fabrication includes obtaining a geometric characteristic of a defect on a chip and obtaining design data of the chip, where the design data is associated with the defect. The method further includes determining a criticality factor of the defect based on the geometric characteristic and the design data, and outputting the criticality factor.

Method and apparatus for determining factors for design consideration in yield analysis

In one embodiment, an inline defect analysis method includes receiving geometric characteristics of individual defects and design data corresponding to the individual defects, determining which of the individual defects are likely to be nuisance defects using the geometric characteristics and the corresponding design data, and refraining from sampling the defects that are likely to be nuisance defects.

Inline defect analysis for sampling and SPC

Described herein is a method and apparatus for performing calibrations on robotic components. In one embodiment, a method for performing robotic calibrations includes moving the calibrating device across a target (e.g., a wafer chuck). Next, the method includes measuring distances between light spots from the sensors and a perimeter of the target using the sensors located on the calibrating device. Next, the method includes determining a displacement of the calibrating device relative to a center of the target. Then, the method includes determining a rotation angle of the calibrating device relative to a system of coordinates of the target. Next, the method includes calibrating a robot position of the robot based on the displacement and rotation angle of the calibrating device with respect to the target.

Method and apparatus for robot calibrations with a calibrating device

In one embodiment, a method for providing a user interface to graphically indicate a cause for fault-related events includes providing a user interface to illustrate a plurality of fault-related events for a plurality of recipes performed on a plurality of manufacturing process hardware tools, presenting in the user interface the plurality of recipes in a first axis and the plurality of manufacturing process hardware tools in a second axis, and graphically indicating in the user interface whether the plurality of fault-related events were caused by one of the plurality of manufacturing process hardware tools or one of the plurality of recipes performed on the one manufacturing process hardware tools.

Software application to analyze event log and chart tool fail rate as function of chamber and recipe

Described herein is a method and system for performing calibrations on robotic components. In one embodiment, a method for performing robotic calibrations includes manually calibrating a center of a robot blade aligned with respect to a target. The method further includes recording a first positional value of the center of the robot blade aligned with respect to a camera. The method further includes automatically determining a second positional value of the center of the robot blade aligned with respect to the camera. The method further includes automatically recalibrating the robot blade based on an offset between the second positional value and the first positional value exceeding a tolerance offset from the first positional value.

Method and system for robot calibrations with a camera

In one embodiment, a method for predicting yield during the design stage includes receiving defectivity data identifying defects associated with previous wafer designs, and dividing the defects into systematic defects and random defects. For each design layout of a new wafer design, yield is predicted separately for the systematic defects and the random defects. A combined yield is then calculated based on the yield predicted for the systematic defects and the yield predicted for the random defects.

Stage yield prediction

In one embodiment, a method for predicting yield includes calculating a criticality factor (CF) for each of a plurality of defects detected in an inspection process step of a wafer, and determining a yield-loss contribution of the inspection process step to the final yield based on CFs of the plurality of defects and the yield model built for a relevant design. The yield-loss contribution of the inspection process step is then used to predict the final yield for the wafer.

Dynamic inline yield analysis and prediction of a defect limited yield using inline inspection defects

Methods and apparatus for categorizing defects on workpieces, such as semiconductor wafers and masks used in lithographically writing patterns into such wafers are provided. For some embodiments, by analyzing the layout in the neighborhood of the defect, and matching it to similar defected neighborhoods in different locations across the die, defects may be categorized by common structures in which they occur.

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San Jose, CA, United States of America

Rinat Shimshi