Altera Corporation

Rina Raman

Richard G Cliff

Srinivas T Reddy

Bruce B Pedersen

Joseph Huang

Kerry S Veenstra

L Todd Cope

David Wolk Mendel

Christopher F Lane

David Edward Jefferson

Francis B Heile

Craig S Lytle

Robert Richard Noel Bielby

Chiakang Sung

Andreas Papaliolios

Richard Shaw Terrill

Robert R Bielby

A programmable logic array integrated circuit device includes a plurality of regions of programmable logic disposed on the device in a two-dimensional array of intersecting rows and columns. Interconnection conductors are associated with each row and column. The interconnection conductors associated with each row include some that extend continuously along the entire length of the row and some that extend continuously along only the left or right half of the row. To increase the flexibility with which the logic regions can be connected to the row and column conductors, adjacent regions are paired and circuitry is provided for allowing the outputs of each pair to be swapped for driving the row and column conductors. Registers in logic regions can still be used for other purposes when not being used to register the main combinatorial outputs of the logic regions. Many other enhanced features are also provided.

Programmable logic array integrated circuit devices

Programmable logic array devices are programmed from programming devices in networks that facilitate programming any number of such logic devices with programs of any size or complexity. The source of programming data and control may be a microprocessor or one or more serial EPROMs, one EPROM being equipped with a clock circuit. Several parallel data streams may be used to speed up the programming operation. A clock circuit with a programmably variable speed may be provided to facilitate programming logic devices with different speed characteristics. The programming protocol may include an acknowledgment from the logic device(s) to the programming data source after each programming data transmission so that the source can automatically transmit programming data at the speed at which the logic device is able to accept that data.

Techniques for programming programmable logic array devices

A programmable logic array integrated circuit device includes a plurality of regions of programmable logic disposed on the device in a two-dimensional array of interesting rows and columns. Interconnection conductors are associated with each row and column. The interconnection conductors associated with each row include some that extend continuously along the entire length of the row and some that extend continuously along only the left or right half of the row. To increase the flexibility with which the logic regions can be connected to the row and column conductors, adjacent regions are paired and circuitry is provided for allowing the outputs of each pair to be swapped for driving the row and column conductors. Registers in logic regions can still be used for other purposes when not being used to register the main combinatorial outputs of the logic regions. Many other enhanced features are also provided.

Programmable logic array intergrated circuit devices

Programmable logic array devices are programmed from programming devices in networks that facilitate programming any number of such logic devices with programs of any size or complexity. The source of programming data and control may be a microprocessor or one or more serial EPROMs, one EPROM being equipped with a clock circuit. Several parallel data streams may be used to speed up the programming operation. A clock circuit with a programmably variable speed may be provided to facilitate programming logic devices with different speed characteristics. The programming protocol may include an acknowledgement from the logic device(s) to the programming data source after each programming data transmission so that the source can automatically transmit programming data at the speed at which the logic device is able to accept that data.

An improved architecture and method of operation for providing redundancy in programmable logic devices. Spare columns or rows of logic blocks 115 and switch boxes 140 are employed to replace columns or rows of logic blocks containing one or more defective logic blocks. Associated logic enable the device to bypass a column or row of logic blocks 115 containing one or more defective logic blocks 115 and to switch in a spare column or row of defect-free logic blocks 115 as replacement.

Implementation of redundancy on a programmable logic device

A programmable, integrated circuit, logic array device has several regular logic groups and at least one spare logic group. If any of the regular logic groups is defective, the spare logic group is used to make up for the defective logic group. To accomplish this, programming and data input signals that would normally go to the defective logic group are redirected to another logic group. The data output signals of the other group are substituted for the data output signals of the logic group that would normally have received the programming and data input signals that were redirected to the other logic group.

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Fremont, CA, United States of America

Rina Raman