International Business Machines Corporation

Rina Kipnis

Vadim Liberchuk

Oded Katz

Christopher B Reynolds

Ofer Geva

Yaniv Maroz

Joseph H Underwood

Lansing D Pickup

Alex Raphayevich

Asaf Regev

William R Andersen

Ido Geldman

Generating reports for critical path evaluation and tuning. A predetermined critical path in a circuit design is detected. The predetermined critical path includes a plurality of interconnects between at least two macros. At least one output or at least one input is detected for each of the at least two macros associated with the predetermined critical path. Additionally, a routing description and a buffer location corresponding to the predetermined critical path are detected and a reduced layout design is built. The reduced layout design includes the predetermined critical path and the at least two macros. Furthermore, a timing report is generated based on the reduced layout design, and a circuit based on the circuit design is manufactured in response to detecting the timing report based on the reduced layout design satisfies a predetermined condition.

Modifying circuits based on timing reports for critical paths

In some examples, a system for modifying circuit can include a processor to detect a previous routed top level circuit design that was proven to close timing within a predetermined range and congestion below a threshold level. The processor can also detect a new pin to be added to a new circuit design and detect user input indicating a bounding box corresponding to a new macro boundary in the previous routed top level circuit design. Additionally, the processor can identify a location of a net in the previous circuit design corresponding to the new pin, wherein the new pin is placed at an intersection between the net and the bounding box. Furthermore, the processor can manufacture a circuit based on the previous circuit design and the placement of the new pin at the intersection between the net and the bounding box.

Modifying a circuit design based on pre-routed top level design

A computer-implemented method identifies at least one proprietary geometric figure from a plurality of geometric figures within a design data layout format file. The proprietary geometric figure in the design data layout format file may be replaced with a placeholder geometric figure. Cell names and connection names associated with the proprietary geometric figure are renamed from a netlist file that defines electrical connections between the geometric figures with obfuscating names. A modified design data layout format file may be generated that includes the placeholder geometric figure and a modified netlist file including the obfuscating names. The modified file enables IC designers to complete their design and checking activities, but inhibits reverse-engineering of the proprietary geometric & netlist data.

Method for providing a secure 'gray box' view proprietary IP

Growing community of inventors

Kiriat Motzkin, Israel

Rina Kipnis