Motorola Corporation

Rina Chowdhury

Olubunmi O Adetutu

Scott K Pozder

Mohammed Rabiul Islam

Matthew Thomas Herrick

Cindy Reidsema Simpson

George F Carney

Ajay Jain

Addi B Mistry

Deborah A Hagen

Marijean E Azrak

Rebecca G Cole

Cindy Kay Goldberg

Kartik Ananthanarayanan

Robert Douglas Mikkola

Edward Acosta

David Moralez Pena

Brett Caroline Baker

An interconnect structure, such as a flip-chip structure, including a base pad and a stud formed on the base pad and extending from the base pad is disclosed. The stud and base pad are formed to be continuous and of substantially the same electrically conductive base material. Typically, a solder structure is formed on the stud wherein the solder structure is exposed for subsequent reflow attachment to another structure. The present invention relates to packaging integrated circuits, more particularly to the structure and processing of a stud and bump without the standard under bump metallurgy.

Method and apparatus for manufacturing an interconnect structure

A method for electroplating a copper layer (,) over a wafer (,) powers a cathode of an electroplating system (,) in a manner that obtains improved copper interconnects. A control system (,) powers the cathode of the system (,) with a mix of two or more of: (i) positive low-powered DC cycles (,or,); (ii) positive high-powered DC cycles (,or,); (iii) low-powered, pulsed, positive-power cycles (,or,); (iv) high-powered, pulsed, positive-powered cycles (,or,); and/or (v) negative pulsed cycles (,or,). The collection of these cycles functions to electroplate copper or a like metal (,) onto the wafer (,). During electroplating, insitu process control and/or endpointing (,or,) is performed to further improve the resulting copper interconnect.

Method for forming a copper layer over a semiconductor wafer

A method for forming a copper interconnect begins by depositing a barrier layer (,) within an in-laid region (,). An edge exclusion protection layer (,) is formed over the barrier layer (,), and this layer (,) is processed so that it only lies within the edge exclusion region (,) of the wafer. The layer (,) is removed from active area portions of the wafer so that contact resistance of copper interconnects is not affected. Wet surface processing is used to form a catalyst (,) on the wafer surface to enable electroless copper plating within active areas of the wafer to form a copper seed layer (,). The layer (,) is not formed in an edge exclusion region (,). Electroplating is then used to thicken the copper material to form a copper layer (,) over the layer (,) wherein the in-laid copper interconnect is completed.

Method for protecting the edge exclusion of a semiconductor wafer from copper plating through use of an edge exclusion masking layer

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Austin, TX, United States of America

Rina Chowdhury