Semiconductor Components Industries, LLC

Ami Semiconductor, Inc.

On Semiconductor

Riley Beck

Kent D Layton

Scott R Grange

Matthew Austin Tyler

Rishi Pratap Singh

Bruce G Armstrong

Sanath Kumar Kondur Surya Kumar

Aaron Shreeve

Kent Layton

Implementations of ground fault circuit interrupter (GFCI) self-test circuits may include: a current transformer coupled to a controller, a silicon controlled rectifier (SCR) test loop coupled to the controller, a ground fault test loop coupled to the controller, and a solenoid coupled to the controller. The SCR test loop may be configured to conduct an SCR self-test during a first half wave portion of a phase and the ground fault test loop may be configured to conduct a ground fault self-test during a second half wave portion of a phase. An SCR may be configured to activate the solenoid to deny power to a load upon one of the SCR self-test or the ground fault self-test being identified as failing.

Ground fault interrupter self test circuits and related methods

Implementations of fault detection circuits may include a first current transformer coupled to a second current transformer, a positive feedback circuit including the first current transformer, the second current transformer, a first switch, and one of a comparator, an amplifier, and an inverter. The circuit may also include a plurality of logic gates that may be coupled with the positive feedback circuit. The positive feedback circuit may be configured to oscillate upon detecting a ground neutral fault and to send a fault signal to the plurality of logic gates. The plurality of logic gates may be configured to analyze the fault signal and open the first switch. The plurality of logic gates may be further configured to identify whether the fault signal represents one of a true fault or a noise fault by analyzing the output of the positive feedback circuit after the first switch has been opened.

Fault detection circuit and related methods

Aspects of an electrical safety device that provides detection of miswiring of line and load connection pairs are presented. In an example, the device includes a differential current detector through which are routed a live current path and a neutral current path coupling the line and load connection pairs. The device also includes a selectable conducting path that, when selected, circumvents the differential current detector while coupling one of a line live connection to a load live connection or a line neutral connection to a load neutral connection of the connection pairs. The device further includes a control circuit that determines, via the differential current detector, while the conducting path is selected, a differential current defined by a difference in currents on the live and neutral current paths, and interrupts at least one of the live and neutral current paths in response to the differential current not exceeding a threshold value.

Electrical safety device miswire detection

A single wound single current transformer impedance measurement circuit for determining a circuit element parameter in a ground fault circuit interrupter circuit. The circuit includes a transconductance amplifier having first and second input terminals and first and second output terminals. In an embodiment, a first detector has input terminal coupled to the first output terminal of the transconductance amplifier and another input terminal coupled for receiving a first electrical signal. A second detector has a terminal coupled to the second output terminal of the transconductance amplifier and an input terminal coupled for receiving the first electrical signal. Alternatively, the second detector has an input terminal coupled to the first output terminal of the transconductance amplifier and another input terminal coupled for receiving the first electrical signal.

Single wound current transformer impedance measurement circuit

A method and circuit for dynamically correcting offsets associated with an AC power system. In an embodiment, a first offset current generated in response to a ground to neutral fault stimulus is decreased and a second offset current generated in response to a differential fault stimulus is decreased. In another embodiment, the circuit includes an offset correction circuit that has one of a chopper circuit or an auto-zeroing circuit. An amplifier is connected to the offset correction circuit and an output connected to the offset correction circuit. A signal generator is switchably coupled to a first input of the offset correction circuit and a bias generator is switchably coupled to the first input of the offset correction circuit.

Ground fault circuit interrupter and method

A ground fault interrupter circuit and a method for operating a ground fault interrupter that includes configuring the ground fault interrupter to perform a plurality of self tests. The ground fault interrupter may be configured to perform a ground fault self test, a grounded-neutral self test, and a trip circuit self test.

A method for operating a ground fault circuit interrupter. In accordance with an embodiment, an operating parameter of the ground fault circuit interrupter can be adjusted in response to an alternating current line signal and a reference signal. In accordance with another embodiment a plurality of indicator signals are generated in response to an alternating current signal. The indicator signals are used to generate one or more control signals and at least one of the control signals is used to control a control a ground fault circuit interrupter.

A method and circuit for determining a circuit element parameter in a ground fault circuit interrupter circuit. An electrical signal provided to a first node is used to generate another electrical signal at a second node. The electrical signal at the second node is multiplexed with a modulation signal to generate a modulated signal that is then filtered and converted into a digital representation of a portion of the circuit element parameter. The electrical signal at the second node is multiplexed with the modulation signal after it has been phase shifted to produce a modulated signal that is filter and converted into a digital representation of another portion of the circuit element parameter. In another aspect, a slope based solenoid self-test method is used for self-testing in a GFCI circuit. Alternatively, a method for determining a wiring fault is provided using a digital filter.

Impedance measuring circuit

A method for determining a circuit element parameter in a ground fault circuit interrupter circuit. An electrical signal provided to a first node is used to generate another electrical signal at a second node. The electrical signal at the second node is multiplexed with a modulation signal to generate a modulated signal that is then filtered and converted into a digital representation of a portion of the circuit element parameter. The electrical signal at the second node is multiplexed with the modulation signal after it has been phase shifted to produce a modulated signal that is filter and converted into a digital representation of another portion of the circuit element parameter. In another aspect, a slope based solenoid self-test method is used for self-testing in a GFCI circuit. Alternatively, a method for determining a wiring fault is provided using a digital filter.

Method for determining a circuit element parameter

A method and circuit for detecting and clamping current in a ground fault circuit interrupter circuit. In accordance with an embodiment the circuit includes an amplifier connected to a switch, where in the amplifier has an input connected to a first conduction terminal of the switch through a resistor and another input connected to a second conduction terminal of the switch. An output of the amplifier is connected to a control terminal of the switch. The circuit may include a ground fault circuit interrupter engine having an input connected to the first conduction terminal of the switch and another second input connected to the second conduction terminal of the switch.

Current saturation detection and clamping circuit and method

An integrated high side switch with multi-fault protection. When a fault condition is detected, the switch is turned off. The switch includes a pair of transistors that are connected such that the source of the first transistor is connected with the source of the second transistor. The drain of the first transistor is thus connected to the supply voltage. A first current mirror generates a current sense output. A second current mirror generates an internal current to detect an over current fault condition. The transistors in the current mirrors are connected like the switch transistors. A high voltage operational amplifier and a transistor are used as feedback to insure that the voltage at the output of the current mirrors matches the voltage at the output of the switch. This ensures that the current mirrors generate scaled versions of the current flowing through the switch.

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Eagle Mountain, UT, United States of America

Riley Beck