Renesas Electronics Corporation

Nec Corporation

Nec Electronics Corporation

Rika Ono

Masahiro Suzuki

Hitoshi Suzuki

Takayuki Miura

Junichi Sato

Koichi Sato

When generating a source code executed by a multi-core processor in order to verify performance of a control system, a device generates the source code as an object of execution by the multi-core processor from a control model, performs cooperative simulation, and measures an execution time of a program in the multi-core processor in the cooperative simulation.

Performance verification device for verifying performance of program, method, and recording medium having program recorded thereon for causing computer to perform the method

A memory control system includes a memory connected to a memory bus, the memory including a plurality of access areas, a memory controller connected to the memory bus, a plurality of registers corresponding to the plurality of access areas, each of the plurality of registers configured to set an access permission or prohibition for a corresponding access area, a CPU (Central Processing Unit) configured to issue a first access request for accessing one of the plurality of access areas, and a memory access controller configured to determine whether an access to the memory is permissible or prohibited using the first access request and the plurality of registers, the memory access controller outputting a second access request in accordance with a determination result.

Microcomputer and method for controlling memory access

A data processing apparatus includes an instruction execution section, a protection control information storage section that stores protection control information that includes first protection information, and second protection information that is independent of the first protection information, an instruction protection information storage section that stores instruction protection information for specifying a partial address space of an instruction address space in which to store instructions that are executable by the instruction execution section, a data protection information storage section that stores data protection information for specifying partial address spaces of a data address space in which to store operands to be usable by the instruction execution section, and a protection violation determination section which, when the first protection information includes a first value, makes a determination as to whether to permit the instruction execution section to access the instruction address space according to the instruction protection information.

Data processing apparatus and address space protection method

A microcomputer including a CPU, a plurality of protection information storages configured to store memory protection information specifying an access permission state or access prohibited state to a memory space by a program executed by the CPU, a memory access control apparatus configured to determine whether or not to allow a memory access request from the CPU according to the memory protection information, and a reset apparatus configured to output a reset signal to the plurality of protection information storages according to a reset request output from the CPU according to a switching of programs executed by the CPU. Each of the plurality of protection information storages is set to a second memory protection state according to the reset signal from a first memory protection state.

A data processing apparatus includes: an instruction execution section; an instruction protection information storage section that stores instruction protection information for specifying at least one partial address space in an instruction address space for storing instructions executed by the instruction execution section; a data protection information storage section that stores data protection information for specifying multiple partial address spaces in a data address space for storing operands for use in an operation of the instruction execution section; and a protection violation determination section that determines whether to permit access from the instruction execution section based on setting of the instruction and data protection information storage sections. The data processing apparatus selectively invalidates protection of the instruction address space using the instruction protection information storage section, independently of protection of the data address space using the data protection information storage section.

A microcomputer includes a CPU, a protection information storage configured to store memory protection information specifying an access permission or a prohibited state to a memory space by a program executed by the CPU, a memory access control apparatus configured to determine whether or not to allow a memory access request from the CPU according to the memory protection information, and a reset apparatus configured to invalidate the memory protection information stored in the protection information storage according to a reset request signal output from the CPU to a switching of programs executed by the CPU, the reset request signal being based on a state of execution of the program by the CPU. The reset apparatus sets all valid bit storing fields of a plurality of protection setting registers of the protection information storage to invalid state in response to the reset request signal output by the CPU.

A microcomputer includes a CPU, a protection information storage configured to store memory protection information specifying an access permission or prohibited state to a memory space by a program executed by the CPU, a memory access control apparatus configured to determine whether or not to allow a memory access request from the CPU according to the memory protection information and a reset apparatus configured to invalidate the memory protection information stored in the protection information storage according to a reset request signal output from the CPU.

A instruction execution part of an information processing device outputs an access request including a first address information to specify an access destination based on an execution of an access command of an address space in a memory. The instruction execution part also outputs a check request including a second address information to specify a stack pointer point after extension based on an execution of a stack extension command to extend a stack included in the address space in the memory by updating a stack pointer. A protection violation detection section of the information processing device detects whether the access destination includes the plurality of the partial spaces by collating the first information with the memory protection information stored in the memory protection information storage section.

Information processing apparatus and method of updating stack pointer

In the translation of a source program to an object program, callee side functions that overlap in cache memory and are called by the same caller side function are detected, and all but one of the overlapping callee side functions called by a given caller side function are replaced with a replica of the original callee side function that will be stored in the cache in a non-overlapping position. The resulting set of callee side functions called by the caller side function are non-overlapping when stored in the cache, and thus the thrashing problem is avoided. This procedure may be repeated a predetermined number of times, or until all instances of overlap have been eliminated through the use of replicated callee side functions.

Language processing method and language processing system improving use efficiency of cache memory

A language processing method detects function call in a source program by static analysis, inserts a branching code to profile process per function call detected in the source program and setting a region of a table storing number of times of corresponding function call per an identification number of call pair in function call, executes translation of the source program inserted the branching code to the profiling process, and increments number of function call of the table with taking the identification number corresponding to kind of call pair in corresponding function call, as index, when the inserted profiling process is present.

Language processing system and language processing method enabling reduction of memory region and overhead in profile information collection of computer

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Tokyo, Japan

Rika Ono