Hitachi, Ltd.

Elpida Memory, Inc.

Renesas Technology Corp.

Renesas Electronics Corporation

Other

Hitachi Ulsi Systems Co., Ltd.

Centre National De La Recherche Scientifique

Hitachi-high-technologies Corporation

Tohoku University

Ps4 Luxco S.a.r.l.

Universite Paris-sud Xi

Riichiro Takemura

Tomonori Sekiguchi

Kazuhiko Kajigaya

Takeshi Sakata

Takayuki Kawahara

Satoru Akiyama

Katsutaka Kimura

Norikatsu Takaura

Hideyuki Matsuoka

Tsugio Takahashi

Kiyoo Itoh

Satoru Hanzawa

Shinichi Miyatake

Kazuo Ono

Hiroaki Nakaya

Kenchi Ito

Kenzo Kurotsuchi

Hiroki Fujisawa

Nozomu Matsuzaki

Hiromasa Takahashi

Masahiro Moniwa

Koji Arai

Kenichi Osada

Hiromasa Noda

Kazushige Ayukawa

Motoyasu Terao

Yoshitaka Nakamura

Akira Ide

Akira Kotabe

Yasuhiro Takai

Ryo Nagai

Yoshimitsu Yanagawa

Satoru Yamada

Shinichiro Kimura

Kousuke Okuyama

Osamu Nagashima

Akio Nishida

Kota Funayama

Yasutoshi Yamada

Tatsuya Sakamoto

Isamu Asano

Kazuyuki Miyazawa

Masayuki M Nakamura

Takamasa Suzuki

Tomoyuki Ishii

Soichiro Yoshida

Yuko Watanabe

Takashi Ishigaki

Osamu Tonomura

Norifumi Kameshiro

Takao Watanabe

Hideo Ohno

Shoji Ikeda

Yutaka Shinagawa

Yoshitaka Sasago

Takashi Anazawa

Naohiko Irie

Tatsuo Nakagawa

Masayuki Nakamura

Naoshi Itabashi

Hideo Kasai

Katsuya Miura

Itaru Yanagi

Makoto Mizuno

Takahiro Morikawa

Takahide Yokoi

Hisao Asakura

Junji Shigeta

Claude Chappert

Nobuaki Kohinata

Shinya Kajiyama

Paul Crozat

Thibault Devolder

Joo-von Kim

To a biomolecule measuring apparatus, a semiconductor sensor for detecting ions generated by a reaction between a biomolecular sample and a reagent is set. The semiconductor sensor has a plurality of cells which are arranged on a semiconductor substrate, and each of which detects ions, and a plurality of readout wires. Each of the plurality of cells has an ISFET which has a floating gate and which detects ions, a first MOSFET Mfor amplifying an output from the ISFET, and a second MOSFET Mwhich selectively transmits an output from the first MOSFET to a corresponding readout wire R. Each of the plurality of cells is provided with a third MOSFET Mwhich generates hot electrons in the ISFET and which injects a charge to the floating gate of the ISFET. Here, the second MOSFET and the third MOSFET are separately controlled.

Biomolecule measuring device

In the field of the next generation DNA sequencer, a method for integrating very high sensitive FET sensors having side gates and nanopores as devices used for identifying four kinds of base and for mapping the base sequence of DNA without using reagents, and a semiconductor device having selection transistors and amplifier transistors respectively corresponding to the FET sensors having side gates and nanopores respectively so as to be able to read the variation of a detection current based on the differences among the charges of the four kinds of base without deteriorating the detection sensitivity of the FET sensor, are presented.

Semiconductor device and manufacturing method thereof

Provided is a device that, on the basis of a measurement result of a current that has a low value and a wide distribution, identifies the composition of biological molecules passing through a nanoparticle path. This biomolecule information analysis device obtains a current value by applying an electrical field to biomolecules passing through a gap between a first electrode and a second electrode, and identifies the structure of the biomolecules by integrating the current value and making a comparison with a reference value (see FIG.).

Biomolecule information analysis device

Since a nonvolatile RAM allows random reading and writing operations, an erasing mode is unnecessary. From the system side, however, it is desirable to have the erasing mode because of its nonvolatile characteristic. Moreover, the erasing operation is desirably carried out at high speed with low power consumption. Therefore, memory cell arrays COA and DTA containing a plurality of memory cells MC each having a magnetoresistive element are provided, a series of data is written to the memory cell arrays COA and DTA, and at the time of erasing, an erasing operation is carried out by writing predetermined data only to the memory cell array COA.

Semiconductor storage device and data processing method

There is provided a magnetic memory with using a magnetoresistive effect element of a spin-injection magnetization reversal type, in which a multi-value operation is possible and whose manufacturing and operation are simple. A preferred aim of this is solved by providing two or more magnetoresistive effect elements which are electrically connected in series to each other and by selecting one of the series-connected elements depending on a direction of a current carried in the series-connected elements, a magnitude thereof, and an order of the current thereof for performing the writing operation. For example, it is solved by differentiating plane area sizes of the respective magnetoresistive effect elements which have the same film structure from each other so as to differentiate resistance change amounts caused by respective magnetization reversal and threshold current values required for respective magnetization reversal from each other.

Magnetic memory, method of manufacturing the same, and method of driving the same

An array configuration capable of supplying a necessary and sufficient current in a small area is achieved and a reference cell configuration suitable to temperature characteristics of a TMR element is achieved. In a memory using inversion of spin transfer switching, a plurality of program drivers are arranged separately along one global bit line, and one sense amplifier is provided to one global bit line. A reference cell to which '1' and '0' are programmed is shared by two arrays and a sense amplifier.

Semiconductor device with low voltage programming/erasing operations

There is provided a semiconductor device which includes a plurality of first through-substrate vias that are used to supply power from a first power supply and that penetrate through a substrate structure, and a plurality of second through-substrate vias that are used to supply power from a second power supply different from the first power supply and that penetrate through a substrate structure. The semiconductor device also includes a through-substrate via string composed by the first and second through-substrate vias, in which the first through-substrate vias are located adjacent to one another and the second through-substrate vias are also located adjacent to one another. The through-substrate via string is disposed in the substrate structure for extending in a first direction.

Semiconductor device

A relation between a drive current of a selection transistor of a magnetic memory and a threshold magnetization switching current of the magnetoresistance effect element is optimized. In order to optimize the relation between the drive current of the selection transistor and the threshold magnetization switching current of the magnetoresistance effect elementof the magnetic memory cell, a mechanism-for dropping the threshold magnetization switching current on '1' writing is provided that applies a magnetic field that is in the inverse direction of the pinned layer to the recording layer of the magnetoresistance effect element.

Magnetic memory cell and magnetic random access memory

Semiconductor device with low voltage programming/erasing operation

The disclosed semiconductor recording device achieves multi-valued reading and writing using a spin-injection magnetization-reversal tunneling magnetoresistive element (TMR element). A first current that has at least the same value as that of the element requiring the highest current to reverse the magnetization thereof among a plurality of TMR elements is, in the direction that causes reversal to either a parallel state or an anti-parallel state, applied to a memory cell having the plurality of TMR elements, and then a second current which is in the reverse direction from the first current and of which only the value needed to reverse the magnetoresistance state of at least one TMR element excluding the element requiring the maximum current among the plurality of TMR elements is applied to each, and multi-valued writing is performed.

Semiconductor recording device

A device is disclosed herein, which may be used a level-shift circuit. The device includes first, second and third power supply lines supplied respectively with first, second and third power voltages that are different from one another, first and second input terminals and an output terminal, an output circuit coupled to the first power supply line, the first and second input terminals and the output terminal, a first inverter including an input node coupled to the first input terminal and an output node coupled to the second input terminal, a first transistor coupled in series to the first inverter between the second and third power supply lines, the first transistor being rendered non-conductive to deactivate the first inverter, and a control circuit configured to prevent the output terminal from being brought into an electrical floating state during deactivation of the first inverter.

For example, one memory cell is configured using two memory cell transistors and one phase change element by disposing a plurality of diffusion layers in parallel to a bit-line, disposing gates between the diffusion layers so as to cross the bit-line, disposing bit-line contacts and source contacts alternately to the plurality of diffusion layers arranged in a bit-line direction for each diffusion layer, and providing a phase change element on the source contact. Also, the phase change element can be provided on the bit-line contact instead of the source contact. By this means, for example, increase in drivability of the memory cell transistors and reduction in area can be realized.

A semiconductor device and a method of manufacturing the same with easy formation of a phase change film is realized, realizing high integration and using a phase change film as a memory element. Between a MISFET of a region forming one memory cell and an adjoining MISFET, each MISFET source adjoins in the front surface of an insulating semiconductor substrate. A multi-layer structure of a phase change film and electric conduction film of specific resistance lower than the specific resistance is formed in plan view of the front surface of a semiconductor substrate ranging over each source of both MISFETs, and a plug is stacked thereon. The multi-layer structure functions as a wiring extending and existing in parallel on the surface of the semiconductor substrate, and an electric conduction film sends current in a parallel direction on the surface of the semiconductor substrate.

Semiconductor device and method of manufacturing the same

To write information on a memory cell of SPRAM formed of an MOS transistor and a tunnel magnetoresistive element, the memory cell is supplied with a current in a direction opposite to a direction of a current required for writing the information on the memory cell, and then, the memory cell is supplied with a current required for writing. In this manner, even when the same information is sequentially written on the memory cell, since the currents in the two directions are caused to flow in pairs in the tunnel magnetoresistive element of the memory cell each time information is rewritten, deterioration of a film that forms the tunnel magnetoresistive element can be suppressed. Therefore, reliability of the SPRAM can be improved.

Semiconductor storage device

Growing community of inventors

Tokyo, Japan

Riichiro Takemura