Kabushiki Kaisha Toshiba

Riichi Katoh

Tetsufumi Tanamoto

Shigeki Takahashi

Li Zhang

Tadashi Sakai

Naoharu Sugiyama

Tsutomu Tezuka

Kouhei Morizuka

Atsushi Kurobe

Masao Mashita

Kunio Tsuda

Mamoru Kurata

Taketoshi Suzuki

Yujiro Naruse

Francis Minoru Saba

Takahiko Endo

An inverter comprising four quantum dot cells. When the quantum dot cells are arranged in 9 o'clock direction, 12 o'clock direction and 3 o'clock direction, the quantum dot cell is arranged in 6 o'clock direction.

Quantum effect device

The semiconductor device comprises a first insulating layer formed on the semiconductor substrate, at least one double-deck semiconductor nanocrystal formed on the first insulating layer, the at least one double-deck semiconductor nanocrystal comprising a first semiconductor nanocrystal and a second semiconductor nanocrystal stacked one upon the other via a second insulating layer, and a third insulating layer selectively formed on the first insulating layer so as to cover the at least one double-deck semiconductor nanocrystal.

Semiconductor memory device having multilayer group IV nanocrystal

A semiconductor device which includes, a substrate, an insulating layer formed on the substrate, a silicon layer having an exposed surface constituted by a Si (100) face, the silicon layer being provided with a tapered recess having a bottom at which a part of the silicon layer is remained without exposing the insulating layer, a first conductive region constituted by the silicon layer remaining at the bottom of the tapered recess, a second and a third conductive regions formed on both sides of the tapered recess respectively, a first insulating film formed on an inner surface of the tapered recess, and an electrode formed in the tapered recess. A flow of electron resulting from the tunneling effect from the second conductive region via the first insulating film to the third conductive region is controlled by controlling a voltage to be impressed onto the electrode.

Single-electron semiconductor device

A quantum effect device includes a first layer having a plurality of charge confinement regions, a second layer opposing the first layer and separated from the first layer, the second layer having charges at a high concentration and consisting of a metal layer or a semiconductor layer, and a third layer consisting of an insulating layer or a semiconductor layer having a large band gap between the first layer and the second layer.

An electronic device which includes, a couple of first conduction regions which are capable of confining carriers, a second conduction region having a higher energy level than those of the first conduction regions, and a first electrode for impressing a voltage on the first conduction regions, wherein when a voltage is impressed via the first electrode between the couple of first conduction regions, carriers are caused to move due to a tunneling effect from one of the first conduction regions via the second conduction region to the other of the first conduction regions, and when the voltage impressed between the couple of first conduction regions is removed, carriers are confined mainly in the one of the first conduction regions.

Electronic device

In a very high speed bipolar transistor, an n.sup.+ -type GaAs collector layer and an n-type GaAs collector layer are stacked in an intrinsic transistor region, and an i-type GaAs collector layer is formed around the n.sup.+ -type GaAs collector layer and the n-type GaAs collector layer. An n-type GaAs collector layer is formed on the n.sup.+ -type GaAs collector layer such that a part of the n-type GaAs collector layer extends on the i-type GaAs collector layer. A p-type GaAs external base layer is formed outside the n-type GaAs collector layer. A p.sup.+ -type Al.sub.x Ga.sub.l-x As base layer is formed on the n-type GaAs collector layer. An emitter layer is formed such that it is arranged only in the intrinsic transistor region on the p.sup.+ -type Al.sub.x Ga.sub.l-x As base layer and constitutes a heterojunction together with the base layer. Design trade-off between the cutoff frequency and maximum oscillation frequency of the transistor is eliminated.

Bipolar transistor with an improved collector structure

In a first heterojunction bipolar transistor (HBT) of the present invention, base layers and collector layers are respectively divided into a plurality of layers and one of the base layers provided closer to the collector layer reiogn is set lower in impurity concentration than the other thereof provided closer to an emitter layer, thus solving a problem that thermal histories during epitaxial growth or during processes cause a set impurity distribution to be destroyed due to diffusion and thus a heterojunction is shifted from a p-n junction. Since minority carriers in the base can smoothly flow toward the collector, there can be realized an excellent HBT having a very high current gain and a very high cut-off frequency. In a second HBT of the invention, a base region comprises a first base layer of a low concentration having the same energy band gap as an emitter region and to be changed to a complete depletion layer in a thermally balanced state and a graded second base layer of a high concentration, and the first and second base layers form a heterojunction, thereby realizing an excellent HBT having a high speed performance which can exhibit a sufficient grading effect while preventing deterioration of an emitter-base voltage withstanding characteristic.

Heterojunction bipolar transistor

A heterojunction bipolar transistor comprises an emitter layer made of a material having a band gap larger than that of a base layer and which includes a region subjected to a composition variation so that the band gap is made gradually smaller from inside of the emitter layer into inside of the base layer toward a base/collector junction direction. In the transistor, the emitter layer is made of an InP composition, the base layer is made of a gaInAsP composition which is lattice matched with the InP composition, and a composition ratio .beta. of P to As in a base/emitter junction satisfies an inequality relationship 0.3.ltoreq..beta..ltoreq.0.7.

A double heterojunction bipolar transistor which comprises a first conductivity type emitter layer, a second conductivity type base layer which is in contact with the emitter layer and forms a first heterojunction in conjunction with the emitter layer, and a collector layer which is in contact with the base layer and is made up of a first conductivity type semiconductor layer and a second conductivity type semiconductor layer. The collector layer includes a low-impurity concentration layer which is in contact with the base layer. The low-impurity concentration layer has the same conductivity type as the base layer and has an impurity concentration lower than that of the base layer. The collector layer forms a second heterojunction in conjunction with the base layer. The emitter layer and the collector layer are formed of a semiconductor material having a band gap wider than that of the base layer.

Heterojunction bipolar transistor having double hetero structure

A heterojunction bipolar transistor comprises a first semiconductor layer of a first conductivity type, a second semiconductor layer of the first conductivity type formed on the first semiconductor layer, a third semiconductor layer of a second conductivity type formed on the second semiconductor layer, the first, second and third semiconductor layers serving as a collector, a fourth semiconductor layer of the second conductivity type formed on the third semiconductor layer, the fourth semiconductor layer serving as a base, and a fifth semiconductor layer of the first conductivity type formed on the fourth semiconductor layer, the fifth semiconductor layer serving as an emitter, the fourth and fifth semiconductor layers together forming a heterojunction, and the fifth semiconductor layer having a larger band gap than the fourth semiconductor layer, wherein the first, second, third and fourth semiconductor layers are related as follows: ##EQU1## where N.sub.1, N.sub.2, N.sub.3, and N.sub.4 are impurity concentrations of the first, second, third, and fourth semiconductor layers, respectively, e is the unit charge, .epsilon. is the dielectric constant of the collector, V.sub.bi is the built-in potential between the second and third semiconductor layers, and W.sub.3 is the thickness of the third semiconductor layer.

Growing community of inventors

Yokohama, Japan

Riichi Katoh