Texas Instruments Corporation

Rida Shawky Assaad

Angelo William Pereira

David W Evans

Kae Ann Wong

Jeffrey Anthony Morroni

Gangqiang Zhang

Mark A Wolfe

William Martin Torres Escajadillo

Ming Sun

Terry Lee Mayhugh, Jr

In a switching regulator driver, a sense circuit has a transistor current input and a sense circuit output. A logic circuit has a logic circuit input and first and second outputs. The logic circuit input is coupled to the sense circuit output. A counter has a counter clock input, a counter control input and a counter output. The counter clock input is coupled to the first output. The counter control input is coupled to the second output. The counter is configured to provide a count value at the counter output. A programmable drive strength circuit has a drive strength circuit input and a transistor control output. The drive strength circuit input is coupled to the counter output. The programmable drive strength circuit is configured to adjust a drive current at the transistor control output based on the count value.

System and method for adaptive gate drive current circuit

A converter includes an inductor and a transistor. A sense circuit couples to the transistor. The sense circuit generates a sense signal responsive to a current through the first transistor. A comparator has first and second comparator inputs and a comparator output. The comparator output controls a signal to the transistor's control input. An error amplifier has an error amplifier input and an error amplifier output coupled to the first comparator input. A slope compensation circuit couples to at least one of the error amplifier output or the sense circuit and generates a slope signal. A peak detection sample/hold (PK-S/H) tracks the slope signal and, responsive to the transistor being turned off, samples the slope signal and provides the sampled slope signal on its output. The PK-S/H output couples to whichever of the error amplifier or sense circuit to which the slope compensation circuit is not coupled.

Slope compensation induced offset error cancellation in a peak or valley current mode switching voltage regulator

In a described example, an apparatus includes at least one latch coupled to a first positive supply voltage and to a first negative supply voltage, the latch having a first inverter and a second inverter coupled to one another back to back, to output a first voltage corresponding to a first latch state and a second voltage corresponding to a second latch state responsive to a first set signal and a first reset signal. An isolation circuit is coupled to a second positive supply voltage and to a second negative supply voltage and is coupled to receive a second set signal, and a second reset signal. The second positive supply voltage is independent of the first positive supply voltage. The isolation circuit outputs the first set signal and the first reset signal and includes less than two pairs of drain extended metal oxide semiconductor (DEMOS) transistors.

Transient-insensitive level shifter

A voltage regulator circuit includes a bias circuit having an input and an output. The input of the bias circuit is coupled to an input voltage supply rail. A Zener diode has a cathode coupled to the output of the bias circuit. A resistor network is coupled to the output of the bias circuit. The resistor network includes a first circuit path, which includes a first resistor, connected in parallel with the Zener diode and a second circuit path, which includes a second resistor, coupled between the output of the bias circuit and a node. A current control circuit is coupled to the bias circuit and the resistor network. An output stage has an input and an output. The input of the output stage is coupled to the node.

Multi-mode voltage regulator

In a described example, an apparatus includes at least one latch coupled to a first positive supply voltage and to a first negative supply voltage, the latch having a first inverter and a second inverter coupled to one another back to back, to output a first voltage corresponding to a first latch state and a second voltage corresponding to a second latch state responsive to a first set signal and a first reset signal. An isolation circuit is coupled to a second positive supply voltage and to a second negative supply voltage and is coupled to receive a second set signal, and a second reset signal, the second positive supply voltage being floating with respect to the first positive supply voltage. The isolation circuit outputs the first set signal and the first reset signal and includes less than two pairs of drain extended metal oxide semiconductor (DEMOS) transistors.

Methods and apparatus for DC-DC soft start are disclosed herein, an example DC-DC voltage converter includes at least two transistors to at least charge or discharge an inductor from an input source and to ground respectively, the inductor to output an output voltage. A synchronize and track circuit generates a bias current based on a reference voltage. An amplifier generates an error current based on an output voltage and the reference voltage. An oscillator oscillates at a switching frequency based on the bias current and the error current. A multiplexer selects between (1) a first input signal generated based on the switching frequency, and (2) a second input signal generated based on the switching frequency and the error current, for output as a reset signal. A latch provides a control signal to the at least two transistors based on the reset signal and the switching frequency.

Methods and apparatus for DC-DC soft start

Methods and apparatus for bootstrap capacitor sharing in multilevel DC-DC converters are disclosed. In one example, a bootstrap capacitor voltage of the bootstrap capacitor can be alternately shared between respective control gates of a first high side primary switch and a central high side primary switch of the multilevel DC-DC converter at different times during a duty cycle of the multilevel DC-DC converter. In another example, the bootstrap capacitor voltage can be transferred to drive respective control gates of the first and central high side primary switches and can ensure full gate drive of the first and central high side primary switches to avoid channel resistance degradation thereof, even when the multilevel DC-DC converter is operated in a substantially full duty cycle mode.

Methods and apparatus for full gate drive of multilevel DC-DC converter with full duty cycle operation

A power converter includes a high side device, a low side device connected to the high side device at a switch node, an inductor connected to the high side device and the low side device at the switch node, and a high side driver. The high side driver is configured to drive a gate of the high side device at a first current for a first period of time. In response to the first period of time ending, the high side driver is configured to step down the first current for a second period of time. In response to the second period of time ending, the high side driver is configured to drive the gate of the high side device at the first current.

Adaptive high-side gate drive for ringing mitigation in switching power converters

Methods and apparatus for flying capacitor balancing in multilevel converters are disclosed. Example flying capacitor balancing circuitry can include voltage difference sense and control circuitry and duty cycle timing adjustment circuitry. The voltage difference sense and control circuitry can generate a compensation control signal for the duty cycle timing adjustment circuitry.

Multilevel buck converter with a flying capacitor and charge pump

A system and method for Flex Over or On Suspension (FOS) fault detection under a write gate for magnetic disk drives may employ a flex over suspension fault comparator that compares a predetermined reference threshold to a positive delta of a disk drive write head data stream and outputs a positive or negative FOS fault indication. A max/min buffer detects polarity of a disk drive read/write head and applies a positive buffered delta to the fault comparator. A transition-free window detector triggers the fault comparator to output the fault indication when a transition-free window of zero-value data bits of a predetermined length is detected from the disk drive head, and the transition-free window detector provides a fault validation signal to validate output of the fault comparator when the transition-free window of zero-value data bits of the predetermined length is detected from the disk drive head.

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Murphy, TX, United States of America

Rida Shawky Assaad