Infineon Technologies Flash Gmbh & Co. Kg

Qimonda Flash Gmbh & Co. Kg

Rico Srowik

Giacomo Curatolo

Zeev Cohen

Nimrod Ben-Ari

Marco Götz

Carlo Borromeo

A method of operating an electronic device includes storing a first plurality of bits of digital information in a memory using a first number of memory cells in parallel. The first plurality of bits of digital information are for operating the device when operating parameters are not within a nominal range. The method also includes storing a second plurality of bits of digital information in the memory using a second number of memory cells in parallel. The second plurality of bits of digital information are for operating the device when operating parameters are within a nominal range.

Device with memory and method of operating device

A method of reading memory includes sensing a plurality of memory cells simultaneously and providing a data signal corresponding to one of a plurality of programming states. The plurality of programming states include a number of programming states equal to twice a number of memory cells in the plurality of memory cells. The data signal is processed, providing binary data representative of the data signal. The binary data includes a number of information bits equal to the number of memory cells.

Memory cell

A method and arrangement are provided for programming an electrically erasable programmable read-only memory cell capable of storing at least one information bit. The memory cell has a charge-trapping region. According to the invention, during a first period of time, a fixed voltage is applied to the memory cell to inject and store electrical charge in the charge-trapping region. This period of time is followed by second period of time during which a constant current is applied to the memory cell to complete the programming step. By monitoring a change in voltage during the second period of time, a monitoring of a resulting threshold voltage is possible directly during programming.

Method of programming of a non-volatile memory cell comprising steps of applying constant voltage and then constant current

A cell arrangement comprising a memory cell arranged in parallel to a first capacitor is charged to a first voltage potential. A second capacitor is charged to a second voltage potential, which is higher than the first voltage potential. The second capacitor is connected to the cell arrangement while the voltage over the cell arrangement comprising the first capacitor is kept constant. The resulting current from the second capacitor through the memory cell is used to detect the state of the memory cell.

Growing community of inventors

Dresden, Germany

Rico Srowik