Silicon Laboratories Inc.

Broadcom Corporation

Avago Technologies General IP (singapore) Pte. Ltd.

Ricky Setiawan

Hua Beng Chan

Rex Wong Tak Ying

Obaida Mohammed Khaled Abu Hilal

Rex Tak Ying Wong

Axel Thomsen

Alan Lee Westwick

Ruifeng Sun

Pio Balmelli

Yow Ching Cheng

Adrianus Josephus Bink

Wajid Hassan Minhass

Ben Wee-Guan Tan

Jeffrey Norwood Harrison

Jinghua Zhang

Tak Ying Wong

Seng Poh Ho

In an embodiment, an apparatus includes: an amplifier to compare a reference voltage to a feedback voltage and to output a comparison signal based on the comparison; a first loop circuit coupled to the amplifier to receive the comparison signal and output a first feedback voltage for the amplifier to use as the feedback voltage in a first mode of operation; and a second loop circuit coupled to the amplifier. The second loop circuit may be configured to receive the comparison signal and output a second feedback voltage for the amplifier to use as the feedback voltage in a second mode of operation. The second feedback voltage may be greater than the first feedback voltage, and the second loop circuit may output a regulated voltage based on the comparison signal.

Voltage regulator having minimal fluctuation in multiple operating modes

In one embodiment, an apparatus includes: an amplifier to compare a reference voltage to a feedback voltage and to output a comparison signal based on the comparison; a loop circuit coupled to the amplifier, where the loop circuit is to receive the comparison signal and provide a regulated voltage to the amplifier as the feedback voltage in a first mode of operation, and in a second mode of operation to provide a predetermined feedback ratio point to the amplifier as the feedback voltage; and an output device coupled to the amplifier. The output device may be configured to receive a supply voltage and the comparison signal and output the regulated voltage at an output node based at least in part on the comparison signal.

Providing low power charge pump for integrated circuit

A power amplifier for a radio frequency transceiver including a driver, a disable circuit, and a bias circuit. The driver includes a source node for receiving a drive voltage when enabled and includes an output node that is susceptible to strong blocker signals when disabled. The bias circuit includes first and second bias nodes for driving the voltage level of the source and output nodes, respectively, to suitable bias voltage levels to minimize impact of blocker signals. The disable circuit includes switch circuits to couple the driver to the bias circuit in the disable mode. The bias circuit may include at least one voltage source. The bias circuit may be coupled to a supply voltage and may include a voltage divider coupled between the source and output nodes. The bias circuit may include a source-follower circuit to isolate the bias voltages from variations of the supply voltage.

System and method of improving blocking immunity of radio frequency transceiver front end

In one aspect, an apparatus includes: a first time-to-data converter (TDC) to oversample a first duration of incoming data and hold the oversampled first duration during receipt of a second duration of the incoming data; a second TDC to oversample the second duration of the incoming data and hold the oversampled second duration during receipt of a third duration of the incoming data; a processing circuit coupled to the first and second TDCs, the processing circuit including a first filter to filter the oversampled first duration and the oversampled second duration and generate a control output therefrom; and a digitally controlled oscillator (DCO) coupled to the processing circuit to receive the control output and generate a recovery clock signal therefrom.

Digital oversampling clock and data recovery circuit

In an embodiment, an integrated circuit includes: a voltage regulator to receive a first voltage and regulate the first voltage to output a regulated voltage; a first logic circuit to operate using the regulated voltage; and a regulator control circuit to receive a control signal during a boot of the integrated circuit via a general purpose pad of the integrated circuit and control the voltage regulator to operate in one of an enabled mode and a bypass mode based at least in part on the control signal.

System, apparatus and method for flexible control of a voltage regulator of an integrated circuit

In one aspect, a method includes: determining a power mode of a device; setting a first reference voltage level and a second reference voltage level based at least in part on the power mode; and using at least one of the first reference voltage level and the second reference voltage level for comparison against incoming data.

Controlling a reference voltage for a clock and data recovery circuit

A system, USB Type-C connector and method are provided herein to transmit encoded data across a USB cable from a transmitter circuit included within a transmitting port of a USB Type-C connector. The method described herein may generally include detecting a voltage generated at a configuration channel (CC) pin of a transmitting port of a USB Type-C connector, setting a voltage at an output node of the transmitter circuit equal to the voltage detected at the CC pin before the output node of the transmitter circuit is connected to the CC pin, subsequently connecting the output node of the transmitter circuit to the CC pin, and transmitting the encoded data from the transmitter circuit through the CC pin to the USB cable.

System, USB Type-C connector and method to transmit encoded data

A low-power low-dropout (LDO) voltage regulator device includes an error amplifier, a level-shifter circuit, and an NMOS pass transistor. The error amplifier compares a sampled portion of a regulated output voltage of the LDO voltage regulator with a reference voltage and generates an error signal. The level-shifter circuit is coupled to the error amplifier. The NMOS pass transistor provides the regulated output voltage with low dropout operation. The level-shifter circuit can shift a voltage level of the error signal to facilitate the low dropout operation of the NMOS pass transistor.

Low-power low-dropout voltage regulators with high power supply rejection and fast settling performance

Apparatus and associated methods are disclosed for gain programming or selection with parasitic element compensation. In one exemplary embodiment, an apparatus includes a first circuit that has a first programmable gain, and includes a first set of components having parasitic elements. The apparatus also includes a second circuit that has a second programmable gain, and includes a second set of components having parasitic elements. The apparatus has a gain that is a product of the first and second programmable gains. A gain error because of the parasitic elements of the first and second sets of components is canceled by setting the first programmable gain as a reciprocal of the second programmable gain.

Apparatus for gain selection with compensation for parasitic elements and associated methods

Apparatus and associated methods are disclosed for gain and offset trimming. In one exemplary embodiment, an apparatus includes a first circuit that includes a first transconductance stage to generate a first current. The first circuit has an output offset. The apparatus further includes an offset trim circuit, which includes a second circuit to provide an output voltage selectable from a plurality of voltage values, and a second transconductance stage to generate a second current in response to the output voltage of the second circuit. The output offset of the first circuit is trimmed by adding the second current to the first current.

Growing community of inventors

Singapore, Singapore

Ricky Setiawan