Sun Microsystems, Inc.

Oracle International Corporation

Oracle America, Inc.

Ricki Dee Williams

Michael C Freda

Gary L Gilbert

Ray Ping-kwan Chan

Implementations of the present disclosure involve an apparatus and/or method for a large array of AC coupling/DC blocking capacitors on a printed circuit board (PCB) of a microelectronic circuit. The method provides for the placement of the blocking capacitors (and associated vias) to be placed on/through the PCB in a small area while yielding low crosstalk or interference between the vias. In one particular embodiment, the blocking capacitors are placed on the PCB in an alternating pattern, with a pair of blocking capacitors placed on the top side of the PCB followed by a pair of blocking capacitors on the bottom side of the PCB, and so on. Further, top side capacitor vias may be back-drilled from the bottom side and bottom side capacitor vias may be back-drilled from the top side.

Method for a printed circuit board with an array of high density AC coupling/DC blocking capacitors

A printed circuit board (PCB) is configured to minimize skew between two parallel signal trace portions. The PCB comprises a laminate layer, which includes a fiberglass weave and includes a plastic resin deposited on each face of the fiberglass weave to form a first face and second face of the laminate layer. The fiberglass weave comprises a first set of fiberglass bundles in a first orientation interwoven with a second set of fiberglass bundles in a second orientation. Moreover, the PCB comprises trace a layer that is coupled to the first face of the laminate layer, and includes two or more signal traces. Two parallel trace portions of the two or more signal traces are configured to have a matching orientation and separation distance to a neighboring fiberglass bundle of the fiberglass weave, thereby ensuring that the two parallel trace portions encounter matching dielectric constants from the laminate layer.

Printed circuit board with low propagation skew between signal traces

The present invention provides a method and apparatus for supplying redundant power. The apparatus includes a first power supply adapted to provide a first portion of power. The apparatus further includes a second power supply adapted to provide a second portion of power and a distribution network, wherein the distribution network is adapted to direct the first portion of power and the second portion of power to a first split path adapted to transmit signals in a system.

Method and apparatus for supplying redundant power

The present invention provides management of one or more domains in a processor-based system over a network connection. An apparatus is provided that comprises a first plane adapted to receive a first voltage level and a second plane adapted to receive a second voltage level. The apparatus further comprises a path asymmetrically positioned between the first plane and the second plane, wherein the path is capable of providing the network connection to one or more devices within the processor-based system.

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Temecula, CA, United States of America

Ricki Dee Williams